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ISP1161 full-speed universal serial bus single-chip host and device controller rev. 01 3 july 2001 product data c c 1. general description the ISP1161 is a single-chip universal serial bus (usb) host controller (hc) and device controller (dc) which complies with universal serial bus speci?cation rev 1.1 . these two usb controllers, the hc and the dc, share the same microprocessor bus interface. they have the same data bus, but different i/o locations. they also have separate interrupt request output pins, separate dma channels that include separate dma request output pins and dma acknowledge input pins. this makes it possible for a microprocessor to control both the usb hc and the usb dc at the same time. ISP1161 provides two downstream ports for the usb hc and one upstream port for the usb dc. each downstream port has its own overcurrent (oc) detection input pin and power supply switching control output pin. the upstream port has its own v bus detection input pin. ISP1161 also provides separate wakeup input pins and suspended status output pins for the usb hc and the usb dc, respectively. this makes power management ?exible. the downstream ports for the hc can be connected with any usb compliant usb devices and usb hubs that have usb upstream ports. the upstream port for the dc can be connected to any usb compliant usb host and usb hubs that have usb downstream ports. the dc is compliant with most device class speci?cations such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. ISP1161 is well suited for embedded systems and portable devices that require a usb host only, a usb device only, or a combined and con?gurable usb host and usb device capabilities. ISP1161 brings high ?exibility to the systems that have it built-in. for example, a system that has ISP1161 built-in allows it not only to be connected to a pc or usb hub that has a usb downstream port, but also to be connected to a device that has a usb upstream port such as a usb printer, usb camera, usb keyboard, usb mouse, among others. ISP1161 enables peer-to-peer connectivity between embedded systems. an interesting application example is to connect a ISP1161 hc with a ISP1161 dc. let us see an example of ISP1161 being used in a digital still camera (dsc) design. figure 1 shows ISP1161 being used as a usb dc. figure 2 shows ISP1161 being used as a usb hc. figure 3 shows ISP1161 being used as a usb hc and a usb dc at the same time.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 2 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. fig 1. ISP1161 operating as a usb device. fig 2. ISP1161 operating as a stand-alone usb host. mgt926 m p system memory m p ISP1161 host/ device m p bus i/f usb i/f usb device usb cable usb i/f embedded system pc (host) dsc mgt927 m p system memory m p ISP1161 host/ device m p bus i/f usb host usb cable usb i/f embedded system usb i/f printer (device) dsc
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 3 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 2. features n complies with universal serial bus speci?cation rev 1.1 n combines hc and dc in a single chip n on-chip dc complies with most device class speci?cations n both hc and dc can be accessed by an external microprocessor via separate i/o port addresses n selectable one or two downstream ports for hc and one upstream port for dc n high speed parallel interface to most of the generic microprocessors and reduced instruction set computer (risc) processors (hitachi sh-3 and sh-4, mips-based risc, arm7/9, strongarm, etc.). maximum 15 mbyte/s data transfer rate between microprocessor and the hc, 11.1 mbyte/s data transfer rate between microprocessor and the dc n supports single-cycle burst mode and multiple-cycle burst mode dma operations n up to 14 programmable usb endpoints with 2 ?xed control in/out endpoints for the dc n built in separate fifo buffer ram for hc (4 kbytes) and dc (2462 bytes) n endpoints with double buffering to increase throughput and ease real-time data transfer for both dc transfers and hc isochronous (iso) transactions n 6 mhz crystal oscillator with integrated pll for low emi n controllable lazyclock (24 khz) output during suspend n clock output with programmable frequency (3 to 48 mhz) n software controlled connection to the usb bus (softconnect) on upstream port for the dc n good usb connection indicator that blinks with traf?c (goodlink) for the dc n built-in software selectable internal 15 k w pull-down resistors for hc downstream ports n dedicated pins for suspend sensing output and wakeup control input for ?exible applications n global hardware reset input pin and separate internal software reset circuits for hc and dc fig 3. ISP1161 operating as both usb host and device simultaneously. mgt928 m p system memory m p ISP1161 host/ device m p bus i/f usb i/f usb device usb cable usb cable usb host usb i/f usb i/f embedded system pc (host) usb i/f printer (device) dsc
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 4 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. n operation at either +5 v or +3.3 v power supply input n 8 kv in-circuit esd protection n operating temperature range - 40 to + 85 c n available in two lqfp64 packages (sot314-2 and sot414-1). 3. applications n personal digital assistant (pda) n digital camera n third-generation (3-g) phone n set-top box (stb) n information appliance (ia) n photo printer n mp3 jukebox n game console. 4. ordering information table 1: ordering information type number package name description version ISP1161bd lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 x 10 x 1.4 mm sot314-2 ISP1161bm lqfp64 plastic low pro?le quad ?at package; 64 leads; body 7 x 7 x 1.4 mm sot414-1
philips semiconductors ISP1161 full-speed usb single-chip host and device controller 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. product data rev. 01 3 july 2001 5 of 130 5. block diagram fig 4. block diagram. mgt929 16 15 k w gnd host/ device automux host bus interface device bus interface clock recovery power switching overcurrent detection usb transceiver usb transceiver pll clock recovery goodlink programmable divider philips slave host controller device controller ping ram pong ram voltage regulator internal supply internal reset 3.3 v v cc power-on reset v reg(3.3) v hold1 dgnd gl clkout 7 1, 8, 15, 18, 35, 45, 62 2 usb transceiver itl0 (ping ram) itl1 (pong ram) ISP1161 h_wakeup to/ from microprocessor h_psw1 46 43 41 38 19 v hold2 24 58 57 2 to 7, 9 to 14, 16, 17, 63, 64 40 42 33 22 21 23 60 59 28 27 34 26 25 30 29 37 36 32 56 n.c. 61, 20 44 47 54 55 50 51 52 53 39 48 49 xtal1 xtal2 h_psw2 h_oc1 h_oc2 d_vbus device controller host controller usb bus upstream port usb bus downstream ports h_dm1 h_dp1 h_dm2 h_dp2 d_dm d_dp h_suspend ndp_sel d0 to d15 rd dack2 dack1 eot dreq1 dreq2 int2 int1 d_wakeup d_suspend reset alt ram 6 mhz host bus device bus 4 1.5 k w 3.3 v softconnect agnd cs wr a1 a0 hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 6 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. fig 5. host controller sub block diagram. mgt930 register access dma handler power-on reset itl0 ram atl ram itl1 ram m p handler pdt_list process usb transceiver usb bus h_dp1 h_dm1 h_dp2 h_dm2 philips sie clock recovery m p interface usb interface philips shc core memory block host controller sub-blocks bus i/f host bus i/f frame manage- ment usb state memory management unit fig 6. device controller sub block diagram. mgt931 m p handler dma handler power-on reset ep handler philips sie d_dp usb bus d_dm usb transceiver memory management unit integrated ram bus i/f clock recovery 3.3 v goodlink softconnect device bus i/f device controller sub-blocks
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 7 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description fig 7. pin con?guration lqfp64. ISP1161bd ISP1161bm mgt932 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 d_dm h_psw2 h_psw1 dgnd 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 d1 d0 dgnd n.c. a1 a0 v reg(3.3) agnd v cc h_oc2 h_oc1 h_dp2 h_dm2 h_dp1 h_dm1 d_dp 49 dgnd d2 d3 d4 d5 d6 dgnd d8 d10 d11 d7 d9 d13 dgnd d14 d15 dgnd v hold1 n.c. rd wr v hold2 d12 cs test int2 int1 dack2 dack1 dreq2 dreq1 reset d_suspend dgnd eot ndp_sel xtal2 xtal1 h_suspend h_wakeup d_vbus gl d_wakeup clkout table 2: pin description for lqfp64 symbol [1] pin type description dgnd 1 - digital ground d2 2 i/o bit 2 of bidirectional data; slew-rate controlled; ttl input; three-state output d3 3 i/o bit 3 of bidirectional data; slew-rate controlled; ttl input; three-state output d4 4 i/o bit 4 of bidirectional data; slew-rate controlled; ttl input; three-state output d5 5 i/o bit 5 of bidirectional data; slew-rate controlled; ttl input; three-state output
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 8 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. d6 6 i/o bit 6 of bidirectional data; slew-rate controlled; ttl input; three-state output d7 7 i/o bit 7 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 8 - digital ground d8 9 i/o bit 8 of bidirectional data; slew-rate controlled; ttl input; three-state output d9 10 i/o bit 9 of bidirectional data; slew-rate controlled; ttl input; three-state output d10 11 i/o bit 10 of bidirectional data; slew-rate controlled; ttl input; three-state output d11 12 i/o bit 11 of bidirectional data; slew-rate controlled; ttl input; three-state output d12 13 i/o bit 12 of bidirectional data; slew-rate controlled; ttl input; three-state output d13 14 i/o bit 13 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 15 - digital ground d14 16 i/o bit 14 of bidirectional data; slew-rate controlled; ttl input; three-state output d15 17 i/o bit 15 of bidirectional data; slew-rate controlled; ttl input; three-state output dgnd 18 - digital ground v hold1 19 - voltage holding pin; this pin is internally connected to the v reg(3.3) and v hold2 pins. when the v cc pin is connected to +5 v, this pin will output 3.3 v, hence it should not be connected to +5 v. when the v cc pin is connected to +3.3 v, this pin can either be connected to +3.3 v or left unconnected. in all cases this pin should be decoupled to dgnd. n.c. 20 - no connection cs 21 i chip select input rd 22 i read strobe input wr 23 i write strobe input v hold2 24 - voltage holding pin; this pin is internally connected to the v reg(3.3) and v hold1 pins. when the v cc pin is connected to +5 v, this pin will output 3.3 v, hence it should not be connected to +5 v. when the v cc pin is connected to +3.3 v, this pin can either be connected to +3.3 v or left unconnected. in all cases this pin should be decoupled to dgnd. dreq1 25 o hcs dma request output (programmable polarity); signals to the dma controller that the ISP1161 wants to start a dma transfer; see hchardwarecon?guration register (20h/a0h) table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 9 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. dreq2 26 o dcs dma request output (programmable polarity); signals to the dma controller that the ISP1161 wants to start a dma transfer; see dcs hardware con?guration register (bah/bbh) dack1 27 i hcs dma acknowledge input. active level programmable. see the hchardwarecon?guration register (20h/a0h) dack2 28 i dcs dma acknowledge input. active level programmable. see dcs hardware con?guration register (bah/bbh) int1 29 o hcs interrupt output; programmable level, edge triggered and polarity; see hchardwarecon?guration register (20h, a0h) int2 30 o dcs interrupt output; programmable level, edge triggered and polarity; see dcs hardware con?guration register (bah, bbh) test 31 o test output; this pin is used for test purposes only. reset 32 i reset input (schmitt trigger); a low level produces an asynchronous reset ndp_sel 33 i number of downstream ports: 0 select 1 downstream port 1 select 2 downstream ports only changes the value of the ndp ?eld in the hcrhdescriptora register; there will always be two ports present in the usbslavehost eot 34 i dma master device to inform ISP1161 of end of dma transfer (active level is programmable), see hchardwarecon?guration register (20h/a0h) dgnd 35 - digital ground d_suspend 36 o dcs suspend state indicator output; active level programmable d_wakeup 37 i dcs wake-up input (edge triggered); a low-to-high transition generates a remote wake-up from suspend state gl 38 o goodlink led indicator output (open-drain); the led is default on, blinks off upon usb traf?c; blinking can be disabled by setting bit 1 of mode register to a 1 d_vbus 39 i dcs usb upstream port v bus sensing input h_wakeup 40 i hcs wake-up input (edge triggered); a low-to-high transition generates a remote wake-up from suspend state clkout 41 o programmable clock output (3 to 48 mhz); default 12 mhz h_suspend 42 o hcs suspend state indicator output; active level programmable xtal1 43 i crystal oscillator input (6 mhz); connect a fundamental mode or third-overtone, parallel-resonant crystal or an external clock source (leaving pin xtal2 unconnected) table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 10 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. [1] symbol names with an overscore (e.g. name) represent active low signals. xtal2 44 o crystal oscillator output (6 mhz); connect a fundamental mode or third-overtone, parallel-resonant crystal; leave this pin open when using an external clock source on pin xtal1 dgnd 45 - digital ground h_psw1 46 o power switching control output for downstream port 1; open drain output h_psw2 47 o power switching control output for downstream port 2; open drain output d_dm 48 ai/o usb d- data line for dcs upstream port d_dp 49 ai/o usb d+ data line for dcs upstream port h_dm1 50 ai/o usb d- data line for hcs downstream port 1 h_dp1 51 ai/o usb d+ data line for hcs downstream port 1 h_dm2 52 ai/o usb d- data line for hcs downstream port 2 h_dp2 53 ai/o usb d+ data line for hcs downstream port 2 h_oc1 54 i overcurrent sensing input for hcs downstream port 1 h_oc2 55 i overcurrent sensing input for hcs downstream port 2 v cc 56 - digital power supply voltage input (3.0 to 3.6 v or 4.75 to 5.25 v). this pin connects to the internal 3.3 v regulator input. when connected to +5 v, the internal regulator will output 3.3 v to pins v reg(3.3) ,v hold1 and v hold2 . when connected to 3.3 v, it will bypass the internal regulator. agnd 57 - analog ground v reg(3.3) 58 - internal 3.3 v regulator output; when the v cc pin is connected to +5 v, this pin outputs 3.3 v. when the v cc pin is connected to +3.3 v, then this pin should also be connected to +3.3 v. a0 59 i address input; selects command (a0 = 1) or data (a0 = 0) a1 60 i address input; selects automux switching to dc (a1 = 1) or automux switching to hc (a1 = 0); see ta b l e 3 n.c. 61 - no connection dgnd 62 - digital ground d0 63 i/o bit 0 of bidirectional data; slew-rate controlled; ttl input; three-state output d1 64 i/o bit 1 of bidirectional data; slew-rate controlled; ttl input; three-state output table 2: pin description for lqfp64 continued symbol [1] pin type description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 11 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 7. functional description 7.1 pll clock multiplier a 6 to 48 mhz clock multiplier phase-locked loop (pll) is integrated on-chip. this allows for the use of a low-cost 6 mhz crystal, which also minimizes emi. no external components are required for the operation of the pll. 7.2 bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream using a 4 over-sampling principle. it is able to track jitter and frequency drift as speci?ed by the usb speci?cation rev. 1.1 . 7.3 analog transceivers three sets of transceiver are embedded in the chip: two are used for downstream ports with usb connector type a; one is used for upstream port with usb connector type b.the integrated transceivers are compliant with the universal serial bus speci?cation rev 1.1 . they interface directly with the usb connectors and cables through external termination resistors. 7.4 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de)stuf?ng, crc checking/generation, packet identi?er (pid) veri?cation/generation, address recognition, handshake evaluation/generation. there are separate sie in both the hc and the dc. 7.5 softconnect (in dc) the connection to the usb is accomplished by bringing d + (for high-speed usb devices) high through a 1.5 k w pull-up resistor. in the ISP1161 the 1.5 k w pull-up resistor is integrated on-chip and is not connected to v cc by default. the connection is established through a command sent by the external/system microcontroller. this allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the usb. re-initialization of the usb connection can also be performed without disconnecting the cable. the ISP1161 dc will check for usb v bus availability before the connection can be established. v bus sensing is provided through pin d_vbus. remark: note that the tolerance of the internal resistors is 25%. this is higher than the 5% tolerance speci?ed by the usb speci?cation. however, the overall v se voltage speci?cation for the connection can still be met with a good margin. the decision to make use of this feature lies with the usb equipment designer.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 12 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 7.6 goodlink (in dc) indication of a good usb connection is provided at pin gl through goodlink technology. during enumeration the led indicator will blink on momentarily. when the ISP1161 has been successfully enumerated (the device address is set), the led indicator will remain permanently on. upon each successful packet transfer (with ack) to and from the ISP1161 the led will blink off for 100 ms. during suspend state the led will remain off. this feature provides a user-friendly indicator of the status of the usb device, the connected hub and the usb traf?c. it is a useful ?eld diagnostics tool for isolating faulty equipment. it can therefore help to reduce ?eld support and hotline overhead. 7.7 suspend and wakeup (in dc) ISP1161s dc also can be put into suspended state by toggling bit 5, gosusp, of the mode register. pin d_suspend is used for the dcs suspended state sensing output. the polarity of d_suspend pin can be changed by setting bit 2, pwroff, of the hardware con?guration register. there are some ways to resume ISP1161s dc from the suspended state: ? by usb host, drivers a k-state on the usb bus (global resume) ? by pin d_wakeup or cs. figure 8 shows the timing relationship for dc going into suspended state, and resuming from the suspended state. 8. microprocessor bus interface 8.1 i/o addressing mode ISP1161 provides i/o addressing mode for external microprocessors to access its internal control registers and fifo buffer ram. i/o addressing mode has the advantage of reducing the pin count for address lines and so occupying less microprocessor resources. ISP1161 uses only two address lines: a1 and a0 to access the internal control registers and fifo buffer ram. therefore, ISP1161 occupies only four i/o ports or four memory locations of a microprocessor. external fig 8. ISP1161 dcs suspend and wakeup. mgs782 wakeup gosusp 2 ms 0.5 ms suspend
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 13 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. microprocessors can read or write ISP1161s internal control registers and fifo buffer ram through the parallel i/o (pio) operating mode. figure 9 shows the parallel i/o interface between a microprocessor and ISP1161. 8.2 dma mode ISP1161 also provides dma mode for external microprocessors to access its internal fifo buffer ram. data can be transferred by dma operation between a microprocessors system memory and ISP1161s internal fifo buffer ram. note: the dma operation must be controlled by the external microprocessor systems dma controller (master). figure 10 shows the dma interface between a microprocessor system and ISP1161. ISP1161 provides two dma channels: dma channel 1 (controlled by dreq1, dack1 signals) is for the dma transfer between a microprocessors system memory and ISP1161 hcs internal fifo buffer ram. dma channel 2 (controlled by dreq2, dack2 signals) is for the dma transfer between a microprocessors system memory and ISP1161 dcs internal fifo buffer ram. the eot signal is an external end-of-transfer signal used to terminate the dma transfer. some microprocessors may not have this signal. in this case, ISP1161 provides an internal eot signal to terminate the dma transfer as well. setting the hcdmacon?guration register (21h - read, a1h - write) enables ISP1161s hc internal dma counter for dma transfer. when the dma counter reaches the value that is set in the hctransfercounter (22h - read, a2h - write) register to be used as the byte count of the dma transfer, the internal eot signal will be generated to terminate the dma transfer. fig 9. parallel i/o interface between microprocessor and ISP1161. mgt933 d [ 15:0 ] rd wr cs a2 irq2 micro- processor ISP1161 d [ 15:0 ] m p bus i/f rd wr cs a1 a1 irq1 a0 int1 int2
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 14 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 8.3 microprocessor read/write ISP1161s internal control registers by pio mode 8.3.1 i/o port addressing ta b l e 3 shows ISP1161s i/o port addressing. complete decoding of the i/o port address should include the chip select signal cs and the address lines a1 and a0. however, the direction of the access of the i/o ports is controlled by the rd and wr signals. when rd is low, the microprocessor reads data from ISP1161s data port. when wr is low, the microprocessor writes a command to the command port, or writes data to the data port. figure 11 and figure 12 illustrate how an external microprocessor accesses ISP1161s internal control registers. fig 10. dma interface between microprocessor and ISP1161. mgt934 d [ 15:0 ] rd wr dack1 dreq1 eot micro- processor ISP1161 d [ 15:0 ] m p bus i/f rd wr dack1 dreq1 dack2 dreq2 dack2 dreq2 eot table 3: i/o port addressing port cs [a1:a0] (bin) access data bus width (bits) description 0 0 00 r/w 16 hc data port 1 0 01 w 16 hc command port 2 0 10 r/w 16 dc data port 3 0 11 w 16 dc command port
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 15 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 8.3.2 register access phases ISP1161s register structure is a command-data register pair structure. a complete register access cycle comprises a command phase followed by a data phase. the command (also known as the index of a register) points the ISP1161 to the next register to be accessed. a command is 8 bits long. on a microprocessors 16-bit data bus, a command occupies the lower byte, with the upper byte ?lled with zeros. figure 13 shows a complete 16-bit register access cycle for ISP1161. the microprocessor writes a command code to the command port, and then reads from or writes the data word to the data port. take the example of a microprocessor attempting to read a chips id, which is saved in the hcs hcchipid register (27h, read only) where its command code is 27h, read only. the 16-bit register access cycle is therefore: 1. microprocessor writes the command code of 27h (0027h in 16-bit width) to ISP1161s hc command port 2. microprocessor reads the data word of the chips id (6110h) from ISP1161s hc data port. when a1 = 0, microprocessor accesses the hc. when a1 = 1, microprocessor accesses the dc. fig 11. a microprocessor accessing a hc or a dc via an automux switch. when a0 = 0, microprocessor accesses the data port. when a0 = 1, microprocessor accesses the command port. fig 12. access to internal control registers. mgt935 m p bus i/f host bus i/f device bus i/f automux dc/hc a1 0 1 mgt936 cmd/data switch commands control registers command register data port a0 command port . . . host or device bus i/f 1 0
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 16 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. for ISP1161s es1 (engineering sample: version one), the chips id is 6110h, where the upper byte of 61h stands for ISP1161, and the lower byte of 10h stands for the ?rst version of the ic chip. most of ISP1161s internal control registers are 16 bits wide. some of the internal control registers, however, have 32-bit width. figure 14 shows how ISP1161s 32-bit internal control register is accessed. the complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. in the two data phases, the microprocessor should ?rst read or write the lower 16-bit data, followed by the upper 16-bit data. to further describe the complete access cycles of ISP1161s internal control registers, the status of some pin signals of the microprocessor bus interface are shown in figure 15 and figure 16 for the hc and the dc respectively. fig 13. 16-bit register access cycle. fig 14. 32-bit register access cycle. fig 15. accessing ISP1161 hc control registers. mgt937 read/write data (16 bits) 16-bit register access cycle t write command (16 bits) mgt938 read/write data (lower 16 bits) 32-bit register access cycle t read/write data (upper 16 bits) write command (16 bits) signals valid status cs 0 a1, a0 01 valid status 0 00 valid status 0 00 rd, wr rd = 1, wr = 0 rd = 0 (read) or wr = 0 (write) data bus command code register data (upper word) register data (lower word) rd = 0 (read) or wr = 0 (write) mgt939
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 17 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 8.4 microprocessor read/write ISP1161s internal fifo buffer ram by pio mode since ISP1161s internal memory is structured as a fifo buffer ram, the fifo buffer ram is mapped to dedicated register ?elds. therefore, accessing ISP1161s internal fifo buffer ram is just like accessing the internal control registers in multiple data phases. figure 17 shows a complete access cycle of ISP1161s internal fifo buffer ram. for a write cycle, the microprocessor ?rst writes the fifo buffer rams command code to the command port, and then writes the data words one by one to the data port until half of the transfers byte count is reached. the hctransfercounter register (22h - read, a2h - write) is used to specify the byte count of a fifo buffer rams read cycle or write cycle. every access cycle must be in the same access direction. the read cycle procedure is similar to the write cycle. for ISP1161 dcs fifo buffer ram access, see section 11 . 8.5 microprocessor read/write ISP1161s internal fifo buffer ram by dma mode the dma interface between a microprocessor and ISP1161 is shown in figure 10 . when doing a dma transfer, at the beginning of every burst the ISP1161 outputs a dma request to the microprocessor via the dreq pin (dreq1 for hc, dreq2 for dc). after receiving this signal, the microprocessor will reply with a dma acknowledge to ISP1161 via the dack pin (dack1 for hc, dack2 for dc), and at the same time, do the dma transfer through the data bus. for normal dma mode, the fig 16. accessing ISP1161 dc control registers. signals valid status cs 0 a1, a0 11 valid status 0 10 valid status 0 10 rd = 1, wr = 0 data bus command code register data (upper word) register data (lower word) mgt940 rd, wr rd = 0 (read) or wr = 0 (write) rd = 0 (read) or wr = 0 (write) fig 17. ISP1161s internal fifo buffer ram access cycle. mgt941 read/write data #1 (16 bits) fifo buffer ram access cycle (transfer counter = 2n) t read/write data #2 (16 bits) read/write data #n (16 bits) write command (16 bits)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 18 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. microprocessor must still issue a rd or wr signal to ISP1161s rd or wr pin. (dack only mode does not need the rd or wr signal.) ISP1161 will repeat the dma cycles until it receives an eot signal to terminate the dma transfer. ISP1161 supports both external eot and internal eot signals. the external eot signal is received as input from ISP1161s eot pin: it generally comes from the external microprocessor. the internal eot signal is generated by ISP1161 internally. to select either, set the dma con?guration registers. for example, for the hc, setting bit 2 of the hcdmacon?guration register (21h - read, a1h - write) to 1 will enable the dma counter for dma transfer. when the dma counter reaches the value of hctransfercounter register, the internal eot signal will be generated to terminate the dma transfer. ISP1161 supports either single-cycle burst mode dma operation or multiple-cycle burst mode dma operation. in both ?gures, the dma transfer is con?gured such that dreq is active high and dack is active low. n = 1/2 byte count of transfer data. fig 18. dma transfer for single-cycle burst mode. mgt942 dreq dack d [ 15:0 ] eot data #1 data #2 data #n rd or wr n = 1/2 byte count of transfer data, k = number of cycles/burst. fig 19. dma transfer for multi-cycle burst mode. mgt943 data #1 data #k data #2k data #n data #(k + 1) data #(n - k + 1) dreq dack d [ 15:0 ] eot rd or wr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 19 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 8.6 interrupts ISP1161 has separate interrupt request pins for the usb hc (int1) and the usb dc (int2). 8.6.1 pin con?guration the interrupt output signals have four con?guration modes: ? level trigger, active low ? level trigger, active high ? edge trigger, active low ? edge trigger, active high. figure 20 shows these four interrupt con?guration modes. they are programmable through register settings, which are also used to disable or enable the signals. 8.6.2 hcs interrupt output pin (int1) to program the four con?guration modes of the hcs interrupt output signal (int1), set bits 1 and 2 of the hchardwarecon?guration register (20h - read, a0h - write). bit 0 is used as the master enable setting for pin int1. int1 has many interrupt events. the relationship between pin int1 and its interrupt events is shown as in figure 21 . fig 20. interrupt pin operating modes. mgt944 int active int active clear or disable int (2) int is level triggered, active high int int 167 ns (3) int is edge triggered, active low int active int 167 ns (4) int is edge triggered, active high int active clear or disable int (1) int is level triggered, active low int
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 20 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the interrupt events of the hc m pinterrupt register (24h - read, a4h - write) changes the status of pin int1 when the corresponding bits of the hc m pinterruptenable register (25h - read, a5h - write) and pin int1s global enable bit (bit 0 of the hchardwarecon?guration register) are all set to enable status. however, events that come from the hcinterruptstatus register (03h - read, 83h - write) affect only the opr_reg bit of the hc m pinterrupt register. they cannot directly change the status of pin int1. 8.6.3 dcs interrupt output pin (int2) the dcs interrupt output pin int2s four con?guration modes can also be programmed by setting bit 0 (intpol) and bit 1 (intlvl) of the dcs hardware con?guration register (bbh - read, bah - write). bit 3 (intena) of the dcs mode register (b9h - read, b8h - write) is used as pin int2s global enable setting. figure 22 shows the relationship between the interrupt events and pin int2. each of the indicated usb events is logged in a status bit of the interrupt register. corresponding bits in the interrupt enable register determine whether or not an event will generate an interrupt. interrupts can be masked globally by means of the intena bit of the mode register (see ta b l e 8 0 ). the active level and signalling mode of the int output is controlled by the intpol and intlvl bits of the hardware con?guration register (see ta b l e 8 2 ). default settings after reset are active low and level mode. when pulse mode is selected, a pulse of 166 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. fig 21. hc interrupt logic. mgt945 sof/itl atl all eot opr reg hcsuspend . . . hcupinterrupt register hcupinterruptenable register hcinterruptstatus register hcinterruptenable register clkready sof/itl ie atl ie all eot ie opr reg ie hcsuspend ie clkready ie so sf rd ue fno rhsc so ie sf ie rd ie ue ie fno ie rhsc ie int enable int trigger int polarity hchardwareconfiguration register pulse generator int1 1 0 x x
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 21 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. bits reset, resume, eot and sof are cleared upon reading the interrupt register. the endpoint bits (ep0out to ep14) are cleared by reading the associated endpoint status register. bit bustatus follows the usb bus status exactly, allowing the ?rmware to get the current bus status when reading the interrupt register. setup and out token interrupts are generated after ISP1161s dc has acknowledged the associated data packet. in bulk transfer mode, the ISP1161s dc will issue interrupts for every ack received for an out token or transmitted for an in token. in isochronous mode, an interrupt is issued upon each packet transaction. the ?rmware must take care of timing synchronization with the host. this can be done via the pseudo start-of-frame (psof) interrupt, enabled via bit iepsof in the interrupt enable register. if a start-of-frame is lost, psof interrupts are generated every 1 ms. this allows the ?rmware to keep data transfer synchronized with the host. after 3 missed sof events the ISP1161s dc will enter suspend state. an alternative way of handling isochronous data transfer is to enable both the sof and the psof interrupts and disable the interrupt for each isochronous endpoint. fig 22. dc interrupt logic. mgt946 reset suspnd resume sof ep14 ... ep0in . . . . . . . . . . . . ep0out eot ierst dc interrupt register dc interrupt enable register iesusp ieresm iesof iep14 ... iep0in iep0out ieeot dc device mode register intena intlvl dc hardware configuration register intpol pulse generator int2 1 0
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 22 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9. the usb host controller (hc) 9.1 the hcs four usb states ISP1161s usb hc has four usb states - usb operational, usb reset, usb suspend, and usb resume - that de?ne the hcs usb signaling and bus states responsibilities. the signals are visible to the hc (software) driver via ISP1161 usb hcs control registers. the usb states are re?ected in the hostcontrollerfunctionalstate ?eld of the hccontrol register (01h - read, 81h - write), which is located at bits 7 and 6 of the register. the hc driver can perform only the usb state transitions shown in figure 23 . remark: the software reset in figure 23 is not caused by the hcsoftwarereset command. it is caused by the hostcontrollerreset ?eld of the hccommandstatus register (02h - read, 82h - write). 9.2 generating usb traf?c usb traf?c can be generated only when the ISP1161 usb hc is under the usb operational state. therefore, the hc driver must set the hostcontrollerfunctionalstate ?eld of the hccontrol register before generating usb traf?c. fig 23. ISP1161 hcs usb states. mgt947 usb_operational usb_suspend usb_resume usb_resume write or remote wake-up usb_reset usb_operational write usb_operational write usb_suspend write usb_reset write usb_reset write usb_reset write hardware reset software reset
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 23 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. a simplistic ?ow diagram showing when and how to generate usb traf?c is shown in figure 24 . for greater accuracy, refer to both the universal serial bus speci?cation revision 1.1 about the protocol and ISP1161 usb hcs register usage. ? reset this includes hardware reset by pin reset and software reset by the hcsoftwarereset command (a9h). the reset function will clear all the hcs internal control registers to their reset status. after reset, the hc driver must initialize the ISP1161 usb hc by setting some registers. ? initialize hc it includes: C setting the physical size for the hcs internal fifo buffer ram by setting the hcitlbufferlength register (2ah - read, aah - write) and the hcatlbufferlength register (2bh - read, abh - write) C setting the hchardwarecon?guration register according to requirements C clearing interrupt events, if required C enabling interrupt events, if required C setting the hcfminterval register (0dh - read, 8dh - write) C setting the hcs root hub registers C setting the hccontrol register to move the hc into usb operational state see also section 9.5 . ? entry the normal entry point. the microprocessor returns to this point when there are hc requests. ? need usb traf?c usb devices need the hc to generate usb traf?c when they have usb traf?c requests such as: C connecting to or disconnecting from the downstream ports C issuing the resume signal to the hc to generate usb traf?c, the hc driver must enter the usb transaction loop. fig 24. ISP1161 hc operating ?ow. mgt948 need usb traffic? prepare ptd data in m p system ram initialize hc transfer ptd data into hc fifo buffer ram hc performs usb transactions via usb bus i/f hc informs hcd of usb traffic results hc interprets ptd data exit entry hc state = usb_operational no yes reset
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 24 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. ? prepare ptd data in m p system ram the communication channel between the hc driver and ISP1161s usb hc is in the form of philips transfer descriptor (ptd) data. the ptd data provides usb traf?c information about the commands, status, and usb data packets. the physical storage media of ptd data for the hc driver is the microprocessors system ram. for ISP1161s usb hc, it is the ISP1161s internal fifo buffer ram. the hc driver prepares ptd data in the microprocessors system ram for transfer to ISP1161s hc internal fifo buffer ram. ? transfer ptd data into hcs fifo buffer ram when ptd data is ready in the microprocessors system ram, the hc driver must transfer the ptd data from the microprocessors system ram into ISP1161s internal fifo buffer ram. ? hc interprets ptd data the hc determines what usb transactions are required based on the ptd data that have been transferred into the internal fifo buffer ram. ? hc performs usb transactions via usb bus interface the hc performs the usb transactions with the speci?ed usb device endpoint through the usb bus interface. ? hc informs hcd the usb traf?c results the usb transaction status and the feedback from the speci?ed usb device endpoint will be put back into the ISP1161s hc internal fifo buffer ram in ptd data format. the hc driver can read back the ptd data from the internal fifo buffer ram. 9.3 ptd data structure the philips transfer descriptor (ptd) data structure provides a communication channel between the hc driver and the ISP1161s usb hc. ptd data contains information required by the usb traf?c. ptd data consists of a ptd followed by its payload data, as shown in figure 25 . fig 25. ptd data in fifo buffer ram. mgt949 ptd fifo buffer ram payload data ptd data #1 ptd payload data payload data ptd ptd data #2 ptd data #n top bottom
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 25 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the ptd data structure is used by the hc to de?ne a buffer of data that will be moved to or from an endpoint in the usb device. this data buffer is set up for the current frame (1 ms frame) by the ?rmware, the hc driver. the payload data for every transfer in the frame must have a ptd as a header to describe the characteristic of the transfer. ptd data is dword aligned. 9.3.1 ptd data header de?nition the ptd forms the header of the ptd data. it tells the hc the transfer type, where the payload data should go, and the payload datas actual size. a ptd is an 8-byte data structure that is very important for hc driver programming. table 4: philips transfer descriptor (ptd): bit allocation bit 7 6 5 4 3 2 1 0 byte 0 actualbytes[7:0] byte 1 completioncode[3:0] active toggle actualbytes[9:8] byte 2 maxpacketsize[7:0] byte 3 endpointnumber[3:0] last speed maxpacketsize[9:8] byte 4 totalbytes[7:0] byte 5 directionpid[1:0] totalbytes[9:8] byte 6 format functionaddress[6:0] byte 7
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 26 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. table 5: philips transfer descriptor (ptd): bit description symbol access description actualbytes[9:0] r/w contains the number of bytes that were transferred for this ptd completioncode[3:0] r/w 0000 noerror general td or isochronous data packet processing completed with no detected errors. 0001 crc last data packet from endpoint contained a crc error. 0010 bitstuf?ng last data packet from endpoint contained a bit stuf?ng violation. 0011 datatogglemismatch last packet from endpoint had data toggle pid that did not match the expected value. 0100 stall td was moved to the done queue because the endpoint returned a stall pid. 0101 devicenotresponding device did not respond to token (in) or did not provide a handshake (out). 0110 pidcheckfailure check bits on pid from endpoint failed on data pid (in) or handshake (out) 0111 unexpectedpid received pid was not valid when encountered or pid value is not de?ned. 1000 dataoverrun the amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in maximumpacketsize ?eld of ed) or the remaining buffer size. 1001 dataunderrun the endpoint returned is less than maximumpacketsize and that amount was not suf?cient to ?ll the speci?ed buffer. 1010 reserved - 1011 reserved - 1100 bufferoverrun during an in, the hc received data from an endpoint faster than it could be written to system memory. 1101 bufferunderrun during an out, the hc could not retrieve data from the system memory fast enough to keep up with the usb data rate. active r/w set to logic 1 by ?rmware to enable the execution of transactions by the hc. when the transaction associated with this descriptor is completed, the hc sets this bit to logic 0, indicating that a transaction for this element should not be executed when it is next encountered in the schedule. toggle r/w used to generate or compare the data pid value (data0 or data1). it is updated after each successful transmission or reception of a data packet. maxpacketsize[9:0] r the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. endpointnumber[3:0] r usb address of the endpoint within the function. last(ptd) r last ptd of a list (itl or atl). a logic 1 indicates that the ptd is the last ptd. (low)speed r speed of the endpoint: s = 0 full speed s = 1 low speed
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 27 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9.4 hcs internal fifo buffer ram structure 9.4.1 partitions according to the universal serial bus speci?cation rev 1.1 , there are four types of usb data transfers: control, bulk, interrupt and isochronous. the hcs internal fifo buffer ram is of a physical size of 4 kbytes. this internal fifo buffer ram is used for transferring data between the microprocessor and usb peripheral devices. this on-chip buffer ram can be partitioned into two areas: acknowledged transfer list (atl) buffer and isochronous (iso)transfer list (itl) buffer. the itl buffer is a ping-pong structured fifo buffer ram that is used to keep the payload data and their ptd header for isochronous transfers. the atl buffer is a non ping-pong structured fifo buffer ram that is used for the other three types of transfers. for the itl buffer, it can be further partitioned into itl0 and itl1 for the ping-pong structure. the itl0 buffer and itl1 buffer always have the same size. the microprocessor can put iso data into either the itl0 buffer or the itl1 buffer. when the microprocessor accesses an itl buffer, the hc can take over another itl buffer at the same time. this architecture can improve the iso transfer performance. the host controller driver can assign the logical size for atl buffer and itl buffers at any time, but normally at initialization after power-on reset, by setting the hcatlbufferlength register (2bh - read, abh - write) and hcitlbufferlength register (2ah - read, aah - write), respectively. however, the total length (atl buffer + itl buffer) should not exceed 4 kbytes, the maximum ram size. figure 26 shows the partitions of the internal fifo buffer ram. when assigning buffer ram sizes, follow this formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length the following assignments are examples of legal uses of the internal fifo buffer ram: ? atl buffer length = 800h, itl buffer length = 400h. this is the maximum use of the internal fifo buffer ram. totalbytes[9:0] r speci?es the total number of bytes to be transferred with this data structure. for bulk and control only, this can be greater than maximumpacketsize. directionpid[1:0] r 00 setup 01 out 10 in 11 reserved format r the format of this data structure. if this is a control, bulk or interrupt endpoint, then format = 0. if this is an isochronous endpoint, then format = 1. functionaddress[6:0] r the is the usb address of the function containing the endpoint that this ptd refers to. table 5: philips transfer descriptor (ptd): bit description continued symbol access description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 28 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. ? atl buffer length = 400h, itl buffer length = 200h. this is insuf?cient use of the internal fifo buffer ram. ? atl buffer length = 1000h, itl buffer length = 0h. this will use the internal fifo buffer ram for only atl transfers. ? atl buffer length = 0h, itl buffer length = 800h. this will use the internal fifo buffer ram for only iso transfers. the actual requirement for the buffer ram may not reach the maximum size. you can make your selection based on your application. the following are some calculations of the iso_a or iso_b space for a frame of data: maximum number of useful data sent during one usb frame is 1280 bytes (20 iso packets of 64 bytes). total ram size needed for this is 20 8 + 1280 = 1440 bytes. ? maximum number of packets for different endpoints sent during one usb frame is 150 (150 iso packets of 1 byte). total ram size needed is 150 8 + 150 1 = 1350 bytes. ? the ping buffer ram (itl0) and the pong buffer ram (itl1) have a maximum size of 2 kbytes each. all data needed for one frame can be stored in the ping or the pong buffer ram. when the embedded system wants to initiate a transfer to the usb bus, the data needed for one frame is transferred to the atl buffer or itl buffer. the microprocessor detects the buffer status through the interrupt routines. when the hcbufferstatus register (2ch - read only) indicates that buffer is empty, then the microprocessor can write data into the buffer. when the hcbufferstatus register indicates that buffer is full, that is data is ready on the buffer, the microprocessor needs to read data from the buffer. during every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. however, each of the interrupt types de?ned in this speci?cation can be enabled or disabled by setting the hc m pinterruptenable register bits accordingly. fig 26. hc internal fifo buffer ram partitions. mgt950 not used atl buffer itl0 top bottom itl1 iso data a fifo buffer ram iso data b control/bulk/interrupt data programmable sizes 4 kbytes itl buffer atl
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 29 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the data transfer can be done via pio mode or dma mode. the data transfer rate can go up to 15 mbyte/s. in dma operation, single-cycle or multi-cycle burst modes are supported. for the multi-cycle burst mode, 1, 4, or 8 cycles per burst is supported for ISP1161. 9.4.2 data organization ptd data is used for every data transfer between a microprocessor and the usb bus, and the ptd data resides in the buffer ram. for an out or setup transfer, the payload data is placed just after the ptd, after which the next ptd is placed. for an in transfer, some ram space is reserved for receiving a number of bytes that is equal to the total bytes of the transfer. after this, the next ptd and its payload data are placed (see figure 27 ). remark: the ptd is de?ned for both atl and itl type data transfer. for itl, the ptd data should be put into itl buffer ram, the ISP1161 takes care of the ping-pong action for the itl buffer ram access. the ptd data (ptd header and its payload data) is a structure of dword (double- word or 4-byte) alignment. this means that the memory address is organized in steps of 4 bytes. therefore, the ?rst byte of every ptd and the ?rst byte of every payload data are located at an address which is a multiple of 4. figure 28 illustrates an example in which the ?rst payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15h. the next addresses (16h and 17h) are not multiples of 4. therefore, the ?rst byte of the next ptd will be located at the next multiple-of-four address, 18h. fig 27. buffer ram data organization. mgt952 ptd of out transfer ram buffer payload data of out transfer ptd of in transfer empty space for in total data ptd of out transfer payload data of out transfer top bottom 000h 7ffh
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 30 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9.4.3 operation & c program example figure 29 shows the block diagram for internal fifo buffer ram operations by pio mode. ISP1161 provides one register as the access port for each buffer ram. for the itl buffer ram, the access port is the itlbufferport register (40h - read, c0h - write). for the atl buffer ram, the access port is the atlbufferport register (41h - read, c1h - write). the buffer ram is an array of bytes (8 bits) while the access port is a 16-bit register. therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal buffer ram by two. the lower byte of the access port register corresponds to the data byte at the even location of the buffer ram, and the higher byte in the access port register corresponds to the other data byte at the odd location of the buffer ram. regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see section 8.4 ). when the pointer of the buffer ram reaches the value of the hctransfercounter register, an internal eot signal will be generated to set bit 2, alleotinterrupt, of the hc m pinterrupt register and update the hcbufferstatus register, to indicate that the whole data transfer has been completed. for itl buffer ram, every start of frame (sof) signal (1 ms) will cause toggling between itl0 and itl1 but this depends on the buffer status. if both itl0bufferfull and itl1bufferfull of the hcbufferstatus register are already logic 1, meaning that both itl0 and itl1 buffer rams are full, the toggling will not happen. in this case, the microprocessor will always have access to itl1. fig 28. ptd data with dword alignment in buffer ram. mgt953 payload data (14 bytes) ptd (8 bytes) ptd (8 bytes) 00h top 08h 15h 18h 20h payload data ram buffer
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 31 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. following is an example of a c program that shows how to write data into the atl buffer ram. the total number of data bytes to be transferred is 80 (decimal) which will be set into the hctransfercounter register as 50h. the data consists of four types of ptd data: 1. the ?rst ptd header (in) is 8 bytes, followed by 16 bytes of space reserved for its payload data; 2. the second ptd header (in) is also 8 bytes, followed by 8 bytes of space reserved for its payload data; 3. the third ptd header (out) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0h to fh incrementing by 1; 4. the fourth ptd header (out) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0h to eh incrementing by 2. in all ptds, we assign device address 5 and endpoint 1. actualbytes is always zero (0). totalbytes equals the number of payload data bytes. the following table shows the results after running this program. however, if communication with a peripheral usb device is desired, the device should be connected to the downstream port and pass enumeration. //the example program for writing atl buffer ram #include #include #include //define register commands #define whctransfercounter 0x22 #define whcupinterrupt 0x24 #define whcatlbufferlength 0x2b #define whcbufferstatus 0x2c // define i/o port address for hc #define hcdataport 0x290 #define hccmdport 0x292 //declare external functions to be used unsigned int hcregread(unsigned int windex); void hcregwrite(unsigned int windex,unsigned int wvalue); void main(void) { table 6: run results of the c program example observed items hc not initialized and not under operational state hc initialized and under operational state comments hc m pinterrupt register bit 1 (atlint) 0 1 microprocessor must read atl bit 2 (alleotinterrupt) 1 1 transfer completed hcbufferstatus register bit 2 (atlbufferfull) 1 1 transfer completed bit 5 (atlbufferdone) 0 1 ptd data processed by hc usb traf?c on usb bus no yes out packets can be seen
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 32 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. unsigned int i; unsigned int wcount,wdata; // prepare ptd data to be written into hc atl buffer ram: unsigned int ptddata[0x28]= { 0x0800,0x1010,0x0810,0x0005, //ptd header for in token #1 //reserved space for payload data of in token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1008,0x0808,0x0005, //ptd header for in token #2 //reserved space for payload data of in token #2 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1010,0x0410,0x0005, //ptd header for out token #1 0x0100,0x0302,0x0504,0x0706, //payload data for out token #1 0x0908,0x0b0a,0x0d0c,0x0f0e, 0x0800,0x1808,0x0408,0x0005, //ptd header for out token #2 0x0200,0x0604,0x0a08,0x0e0c //payload data for out token #2 }; hcregwrite(whcupinterrupt,0x04); //clear eot interrupt bit //hcregwrite(whcitlbufferlength,0x0); hcregwrite(whcatlbufferlength,0x1000); //ram full use for atl //set the number of bytes to be transferred hcregwrite(whctransfercounter,0x50); wcount = 0x28; //get word count outport (hccmdport,0x00c1); //command for atl buffer write //write 80 (0x50) bytes of data into atl buffer ram for (i=0;i philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 33 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. return(wvalue); } // // write hc 16-bit registers // void hcregwrite(unsigned int windex,unsigned int wvalue) { outport(hccmdport,windex | 0x80); outport(hcdataport,wvalue); } 9.5 hcs operational model upon power up, the hc driver sets up all operational registers (32-bit). the fslargestdatapacket ?eld (bits 30 to 16) of the hcfminterval register (0dh - read, 8dh - write) and the hclsthreshold register (11h - read, 91h - write) determine the end of the frame for full-speed and low-speed packets. by programming these ?elds, the effective usb bus usage can be changed. furthermore, the size of the itl buffers (hcitlbufferlength, 2ah - read, aah - write) is programmed. in the case when a usb frame contains both iso and at packets, two interrupts will be generated per frame. fig 29. pio access to internal fifo buffer ram. mgt951 commands pointer automatically increments by 2 transfercounter bufferstatus bufferstatus internal eot itlbufferport atlbufferport atl buffer ram (8-bit width) control registers command register data port t eot 1 2 = 0 toggle command port m pinterrupt 22h/a2h 2ch 40h/c0h 41h/c1h 24h/a4h 000h 7ffh 001h itl1 buffer ram (8-bit width) 000h 3ffh 001h itl0 buffer ram (8-bit width) 000h 3ffh 001h a0 host bus i/f 1 0 (16-bit width) sof
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 34 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. one interrupt is issued concurrently with the sof. this interrupt (the itlint is set in the hc m pinterrupt register) triggers reading and writing of the itl by the microprocessor, after which the interrupt is cleared by the microprocessor. next the programmable at interrupt (the atlint is set in the hc m pinterrupt register) is issued, which triggers reading and writing of the itl by the microprocessor, after which the interrupt is cleared by the microprocessor. if the microprocessor cannot handle the iso interrupt before the next iso interrupt, disrupted iso traf?c can result. to be able to send more than one packet to the same control or bulk endpoint in the same frame, an active bit and a totalbytes of transfer ?eld are introduced (see ta b l e 5 ). the active bit is cleared only if all data of the philips transfer descriptor (ptd) are transferred or if a transaction at that endpoint contained a fatal error. if all ptd of the atl are serviced once and the frame is not over yet, the hc starts looking for a ptd with the active bit still set. if such a ptd is found and there is still enough time in this frame, another transaction is started on the usb bus for this endpoint. for iso processing, the host controller driver has also to take care of the bufferstatus register (2ch, read only) for the itl buffer ram operations. after the host controller driver writes iso data into itl buffer ram, the itl0bufferfull or itl1bufferfull bit (depends if it is itl0 or itl1) will be set to logic 1. after the hc processes the iso data in the itl buffer ram then the corresponding itl0bufferdone or itl1bufferdone bit will automatically be set to logic 1. the host controller driver can clear the buffer status bits by a read of the itl buffer ram, and this must be done within the 1 ms frame from which the itl0bufferdone or itl1bufferdone was set. failure to do so will cause the iso processing to stop and a power on reset or software reset will have to be applied to the hc, a usb reset to the usb bus must not be made. for example, in the ?rst frame, for the hcd doing a write of iso-a data into the itl0 buffer. this will cause the bufferstatus register to show that the itl0 buffer is full by setting the itl0bufferfull bit to logic 1. at this stage the host controller driver cannot write iso data into the itl0 buffer ram again. in the second frame, the host controller will process the iso-a data in the itl0 buffer. at the same time, the hcd can write iso-b data into itl1 buffer. when the next sof comes (the beginning of the third frame), both the itl1bufferfull and itl0bufferdone are automatically set to logic 1. in the third frame the hcd has to read itl0 buffer at least two bytes (one word) to clear both the itl0bufferfull and itl0bufferdone bits. if both are not cleared, when the next sof comes (the beginning of the fourth frame) the itl0bufferdone bit will be cleared automatically, but the itl0bufferfull bit remains at logic 1 and the itl0bufferfull bit will be unable to be cleared. this condition will disable the hcd from writing iso data into the itl0 buffer again and iso processing be unable to be carried on. this also applies to the itl1 buffer because the itl0 and itl1 are ping-pong structured buffers. to recover from this state the power on reset or software reset will have to be applied on the hc. time domain behavior in the ?rst example the cpu is fast enough to read back and download a scenario before the next interrupt. note that on the iso interrupt of frame n:
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 35 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. ? the iso packet for frame n + 1 will be written; ? the at packet for frame n + 1 will be written. in the next example, the microprocessor is still busy transferring the at data when the iso interrupt of the next frame (n + 1) is raised. as a result, there will be no at traf?c in frame n + 1. the hc should not raise an at interrupt in frame n + 1. the at part is simply postponed until frame n + 2. on the at n + 2 interrupt the transfer mechanism is back to normal operation. this simple mechanism ensures, among other things, that control transfers are not dropped systematically from the usb in case of an overloaded microprocessor. in the following example the iso part is still being written while the start of frame (sof) of the next frame has occurred. this will result in unde?ned behaviour for the iso data on the usb bus in frame n + 1 (depending on the exact timing data is corrupted or not). the hc should not raise an at interrupt in frame n + 1. fig 30. hc time domain behavior: example 1. mgt954 (frame n) (frame n + 1) (frame n + 2) (frame n + 3) read iso_a(n - 1) write iso_a(n + 1) sof read at(n) write at(n + 1) at interrupt traffic on usb iso interrupt fig 31. hc time domain behavior: example 2. mgt955 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 36 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. control transaction limitations the different phases of a control transfer (setup, data and status) should never be put in the same atl. 9.6 microprocessor loading the maximum amount of data that can be transferred for an endpoint during one frame is 1023 bytes. the number of usb packets that are needed for this batch of data depends on the maximum packet size that is speci?ed. the hc driver has to schedule the transactions in a frame. on the other hand, the microprocessor must have the ability to handle the interrupts coming from hc every 1 ms. it must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the buffer ram in the time between the end of the current frame and the start of the next frame. 9.7 internal 15 k w pull-down resistors for downstream ports there are four internal 15 k w pull-down resistors built in ISP1161 for the two downstream ports: two resistors for each port. these resistors are software selectable by programming bit 12 of the hchardwarecon?guration register (20h - read, a0h - write). when bit 12 is cleared to logic 0, it means that external 15 k w pull-down resistors should be used. bit 12 is set to logic 1 that indicates the internal built in 15 k w pull-down resistors will be used instead of external ones. see figure 33 . this feature is a cost-saving option. however, the power on reset default value is logic 0. if you want to use the internal resistors, the hc driver must check this bit status after every reset, because a reset action will clear this bit regardless of it being a hardware reset or a software reset. fig 32. hc time domain behavior: example 3. mgt956 (frame n) (frame n + 1) (frame n + 2) (frame n + 3)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 37 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9.8 overcurrent detection and power switching control a downstream port provides +5 v power supply to the v bus . the ISP1161 has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. these hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. h_psw1 and h_psw2 are power switching control output pins (active low, open drain) for downstream port 1 and 2, respectively. h_oc1 and h_oc2 are overcurrent detection input pins for downstream ports 1 and 2, respectively. let h_pswn denote either h_psw1 or h_psw2 and h_ocn denote either h_oc1 or h_oc2. figure 34 shows the ISP1161 downstream port power management scheme. using either internal or external 15 k w resistors. fig 33. use of 15 k w pull-down resistors on downstream ports. mgt957 22 w 22 w bit 12 hchardware configuration ISP1161 usb connector d - d + v bus internal 15 k w (2 ) external 15 k w (2 ) 47 pf (2 ) fig 34. downstream port power management scheme. mgt959 1 3 0 reg bit 10 psw oc select oc detect regulator h_ocn h_pswn hc core c/l ISP1161 v cc ( + 5 v or + 3.3 v) hchardware configuration
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 38 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9.8.1 using internal oc detection circuit the internal oc detection circuit can be used only when v cc (pin 56) is connected to a +5 v power supply. the hc driver must set analogocenable, bit 10 of the hchardwarecon?guration register, to logic 1. an application using the internal oc detection circuit and internal 15 k w pull-down resistors is shown in figure 35 , where h_dmn denotes either pin h_dm1 or h_dm2, while h_dpn denotes either pin h_dp1 or h_dp2. in this example, the hc driver must set both analogocenable and the downstreamport15kresistorsel to logic 1. they are bit 10 and bit 12 of the hchardwarecon?guration register, respectively. when h_ocn detects an overcurrent status on a downstream port, h_pswn will output high, a logic 1 to turn off the +5 v power supply to the downstream port v bus . when there is no such detection, h_pswn will output low, a logic 0 to turn on the +5 v power supply to the downstream port v bus . in general applications, we can use a p-channel mosfet (such as php109) as the power switch for v bus . connect the +5 v power supply to the drain pole of the p-channel mosfet, v bus to the source pole, and h_pswn to the gate pole. we call the voltage drop ( d v) across the drain and source poles the overcurrent trip voltage. for the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold of 75 mv. therefore, when the overcurrent trip voltage ( d v) exceeds the voltage threshold, h_pswn will output a high level, logic 1 to turn off the p-channel mosfet. if the p-channel mosfet has a r dson of 150 m w , the overcurrent threshold will be 500 ma. the selection of a p-channel mosfet with a different r dson will result in a different overcurrent threshold.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 39 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 9.8.2 using external oc detection circuit when v cc (pin 56) is connected to the +3.3 v power supply instead of the +5 v power supply, then the internal oc detection circuit cannot be used. an external oc detection circuit must be used instead. nevertheless, regardless of v cc s connections, an external oc detection circuit can be used from time to time. to use an external oc detection circuit, analogocenable, bit 10 of the hchardwarecon?guration register, should be set to logic 0. by default after reset, this bit is already set to logic 0; therefore, the hc driver does not need to clear this bit. figure 36 shows how to use an external oc detection circuit. fig 35. using internal oc detection circuit. mgt960 atx 1 3 0 reg psw oc select oc detect regulator v cc h_ocn d v = + 5 v - v bus h_pswn h_dmn h_dpn hc core c/l sie usb downstream port connector 15 k w (2 ) 47 pf (2 ) 22 w 22 w ISP1161 v bus + 5 v p-ch mosfet (php109) bit 10 bit 12 hchardware configuration hchardware configuration
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 40 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 10. suspend and wakeup (in hc) 10.1 hc suspended state the hc can be put into suspended state by setting the hccontrol register (01h - read, 81h - write). see figure 23 for the hcs ?ow of usb states changes. fig 36. using external oc detection circuit. v o v i oc en v cc h_ocn h_pswn h_dmn h_dpn usb downstream port connector 47 pf (2 ) 22 w 22 w v bus + 3.3 v or + 5 v + 5 v external oc detect mgt961 atx 1 3 0 reg psw oc select oc detect regulator hc core c/l sie 15 k w (2 ) ISP1161 bit 10 bit 12 hchardware configuration hchardware configuration fig 37. ISP1161 suspend and resume clock scheme. mgt958 on on xosc_6mhz (to dc pll) xosc on voltage regulator hc pll hc_clkok hc_rawclk48m hc_enableclock h_wakeup (pin) dc_enableclock cs (pin) hc_needclock pll_lock pll_clkout on digital clock switch hc core hc_clk48mout hchardware configuration bit 11 (suspendclknotstop)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 41 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. with the device in a suspended state it will consume considerably less power by turning off the internal 48 mhz clock, pll and crystal, and setting the internal regulator to power-down mode. the ISP1161 suspend and resume clock scheme is shown in figure 37 . remark: ISP1161 can be put into a fully suspended mode only after both the hc and the dc go into the suspended mode, when the crystal can be turned off and the internal regulator can be put into power-down mode. pin h_suspend is the sensing output pin for hcs suspended state. when the hc goes into suspend state, this pin will output a high level (logic 1). this pin is cleared to low (logic 0) level only when the hc is put into a reset state or operational state (refer to the hccontrol register bits 7 to 6, 01h - read, 81h - write). by setting bit 11, suspendclknotstop, of the hchardwarecon?guration register (20h - read, a0h - write), you can also de?ne such that when the hc goes into suspend state, its internal clock is stopped or kept running. after hc enters the suspend state for 1.3 ms, the internal clock will be stopped if bit suspendclknotstop is logic 0. 10.2 hc wakeup from suspended state there are three methods to wake up the hc from the usb suspend state: hardware wakeup, software wakeup, and usb bus resume. they are described as follows: 10.2.1 wakeup by pin h_wakeup pins h_suspend and h_wakeup provide hardware wakeup, a way of remote wakeup control for the hc without the need to access the hc internal registers. h_wakeup is an external wakeup control input pin for the hc. after the hc goes into suspend state, it can be woken up by sending a high level pulse to pin h_wakeup. this will turn on the hcs internal clock, and set bit 6, clkready, of the hc m pinterrupt register (24h - read, a4h - write). under the suspend state, once pin h_wakeup goes high, after 160 m s, the internal clock will be up. after the internal clock is up, it will be kept running at least 1.14 ms depending on the status of pin h_wakeup. if pin h_wakeup is high, then the internal clock will be kept running. if pin h_wakeup is low, then the internal clock can be kept running for 1.14 ms only, unless the microprocessor sets the hc into operational state during this time. 10.2.2 wakeup by pin cs (software wakeup) during the suspend state, an external microprocessor issues the chip select signal through pin cs to ISP1161. this method of access to ISP1161 internal registers is a software wakeup. 10.2.3 wakeup by usb devices for the usb bus resume, a usb device attached to the root hub port issues a resume signal to the hc through the usb bus, switching the hc from suspend state to resume state. this will also set the resumedetected bit, bit 3 of the hcinterruptstatus register (03h - read, 83h - write).
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 42 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. no matter which method is used to wake up the hc from suspend state, you must enable the corresponding interrupt bits before the hc goes into suspend state so that the microprocessor can receive the correct interrupt request to wake up the hc. 11. the usb device controller (dc) the device controller (dc) in ISP1161 originates from philips isp1181 usb full-speed interface device ic. the functionality is same as isp1181 in 16-bit bus mode. the command and register sets are also the same. refer also to the isp1181 datasheet for a description of the operation of ISP1161s dc. if there is any difference found in isp1181 and ISP1161 datasheet in terms of the dcs functionality, the ISP1161 datasheet supersedes the content in isp1181 datasheet. in general the dc in ISP1161 provides 16 endpoints for usb device implementation. each endpoint can be allocated an amount of ram space in the on-chip ping-pong buffer ram. note: the ping-pong buffer ram for the dc is independent of the buffer ram in the hc. when the buffer ram is full, the dc will transfer the data in the buffer ram to the usb bus. when the buffer ram is empty, an interrupt is generated to notify the microprocessor to feed in the data. the transfer of data between the microprocessor and the dc can be done in parallel i/o (pio) mode or in dma mode. 11.1 dc data transfer operation the following session explains how the dc of ISP1161 handles an in data transfer and an out data transfer. in device mode, ISP1161 acts as a usb device: an in data transfer means transfer from ISP1161 to an external usb host (through the upstream port) and an out transfer means transfer from external usb host to ISP1161. 11.1.1 in data transfer ? the arrival of the in token is detected by the sie by decoding the pid. ? the sie also checks for the device number and endpoint number and veri?es whether they are ok. ? if the endpoint is enabled, the sie checks the contents of the endpoint status register. if the endpoint is full, the contents of the fifo are sent during the data phase, else a nak handshake is sent. ? after the data phase, the sie expects a handshake (ack) from the host (except for iso endpoints). ? on receiving the handshake (ack), the sie updates the interrupt register contents, which in turn generates an interrupt to the microprocessor. the last transaction register (ltr) status is updated and the buffer is set to zero in the endpoint status register. if it fails to get a handshake, a timeout error is generated and the ltr status is updated accordingly. for iso endpoints, the interrupt and ltr status are updated as soon as data are sent, since there is no handshake phase. ? on receiving an interrupt, the microprocessor reads the interrupt register. it will know which endpoint has generated the interrupt and reads the contents of the corresponding endpoint status register. if the buffer is empty, it ?lls up the buffer, so that data can be sent by the sie at the next in token phase.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 43 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 11.1.2 out data transfer ? the arrival of the out token is detected by the sie by decoding the pid. ? the sie also checks for the device number and endpoint number and veri?es whether they are ok. ? if the endpoint is enabled, the sie checks the contents of the endpoint status register. if the endpoint is empty, the data from usb is stored to fifo during the data phase, else a nak handshake is sent. ? after the data phase, the sie sends a handshake (ack) to the host (except for iso endpoints). ? the sie updates the contents of the interrupt register, which in turn generates an interrupt to the microprocessor. the ltr status is updated and the buffer is set to full in the endpoint status register. for iso endpoints, interrupt and ltr status are updated as soon as data is received successfully, since there is no handshake phase. ? on receiving interrupt, the microprocessor reads the interrupt register. it will know which endpoint has generated the interrupt and reads the content of the corresponding endpoint status register. if the buffer is full, it empties the buffer, so that data can be received by the sie at the next out token phase. 11.2 device dma transfer 11.2.1 for out endpoint (external usb host to ISP1161s dc) when the internal dma handler is enabled and at least one buffer (ping or pong) is free, the dreq2 line is asserted. the external dma controller then starts negotiating for the bus with ISP1161. as soon as it has access, it asserts the dack2 line and starts writing data. the burst length is programmable. when the number of bytes equal to the burst length has been written, the dreq2 line is deasserted. as a result, the dma controller deasserts the dack2 line and releases the bus. at that moment the whole cycle restarts for the next burst. when the buffer is full, the dreq2 line will be de-asserted and the buffer is validated (which means that it will be sent to the host when the next in token comes in). when the dma controller terminates the dma transfer by asserting eot, the buffer is also validated (even if it is not full). in auto-reload mode, the dma handler will automatically restart by asserting its dreq2 line as soon as a new buffer is available. if the auto-reload mode is off, then the dma handler will be disabled automatically. for the next dma transfer, the dma handler must be reenabled. 11.2.2 for in endpoint (ISP1161s dc to external usb host) when the internal dma handler is enabled and at least one buffer is full, the dreq2 line is asserted. the external dma controller then starts negotiating for the bus with other parties and as soon as it has access, it asserts the dack2 line and starts reading the data. the burst length is programmable. when the number of bytes equal to the burst length has been read, the dreq2 line is deasserted. as a result, the dma controller deasserts the dack2 line and releases the bus. at that moment the whole cycle restarts for the next burst. when all data are read, the dreq2 line will be deasserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in).
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 44 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. when the dma controller terminates the dma transfer by asserting eot and auto-reload mode is off, the buffer is also cleared (even if not all data are read) and the dma handler is disabled automatically. for the next dma transfer, the dma controller as well as the dma handler must be re-enabled. however in auto-reload mode, the dma handler will automatically restart by reasserting the dreq2 line, without any loss of data. 11.3 endpoint descriptions 11.3.1 endpoints with programmable fifo size each usb device is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ?ow between the host and the device. at design time each endpoint is assigned a unique number (endpoint identi?er, see ta b l e 7 ). the combination of the device address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced. the ISP1161 has 16 endpoints: endpoint 0 (control in and out) plus 14 con?gurable endpoints, which can be individually de?ned as interrupt/bulk/isochronous, in or out. each enabled endpoint has an associated fifo, which can be accessed either via the parallel i/o interface or via dma. 11.3.2 endpoint access ta b l e 7 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support dma access. fifo dma access is selected and enabled via bits epidx[3:0] and dmaen of the dma con?guration register. a detailed description of the dma operation is given in section 12 . table 7: endpoint access and programmability endpoint identi?er fifo size (bytes) double buffering i/o mode access dma mode access endpoint type 0 64 (?xed) no yes no control out [1] 0 64 (?xed) no yes no control in [1] 1 programmable supported supported supported programmable 2 programmable supported supported supported programmable 3 programmable supported supported supported programmable 4 programmable supported supported supported programmable 5 programmable supported supported supported programmable 6 programmable supported supported supported programmable 7 programmable supported supported supported programmable 8 programmable supported supported supported programmable 9 programmable supported supported supported programmable 10 programmable supported supported supported programmable 11 programmable supported supported supported programmable 12 programmable supported supported supported programmable 13 programmable supported supported supported programmable 14 programmable supported supported supported programmable
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 45 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. [1] in: input for the usb host (ISP1161 transmits); out: output from the usb host (ISP1161 receives). [2] the data ?ow direction is determined by bit epdir in the endpoint con?guration register. [3] the total amount of fifo storage allocated to enabled endpoints must not exceed 2462 bytes. 11.3.3 endpoint fifo size the size of the fifo determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared fifo storage, disabled endpoints have zero bytes. ta b l e 8 lists the programmable fifo sizes. the following bits in the endpoint con?guration register (ecr) affect fifo allocation: ? endpoint enable bit (fifoen) ? size bits of an enabled endpoint (ffosz[3:0]) ? isochronous bit of an enabled endpoint (ffoiso). remark: register changes that affect the allocation of the shared fifo storage among endpoints must not be made while valid data is present in any fifo of the enabled endpoints. such changes will render all fifo contents unde?ned .
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 46 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. each programmable fifo can be con?gured independently via its ecr, but the total physical size of all enabled endpoints (in plus out) must not exceed 2462 bytes (512 bytes for non-isochronous fifos). ta b l e 9 shows an example of a con?guration ?tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. table 8: programmable fifo size ffosz[3:0] non-isochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 9: memory con?guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64 byte ?xed) 64 64 control out (64 byte ?xed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt out 16 16 16-byte interrupt in 128 64 double-buffered 64-byte bulk out 128 64 double-buffered 64-byte bulk in
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 47 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 11.3.4 endpoint initialization in response to the standard usb request set interface, the ?rmware must program all 16 ecrs of the ISP1161 in sequence (see ta b l e 7 ), whether the endpoints are enabled or not. the hardware will then automatically allocate fifo storage space. if all endpoints have been con?gured successfully, the ?rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con?guration, the ?rmware must stall the control in endpoint. when reset by hardware or via the usb bus, the ISP1161 dc disables all endpoints and clears all ecrs, except for the control endpoint which is ?xed and always enabled. endpoint initialization can be done at any time; however, it is valid only after enumeration. 11.3.5 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the interrupt register (ir) will be set by the sie. the ?rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit will be cleared by reading the endpoint status register (esr). the esr also contains information on the status of the endpoint buffer. for an out (= receive) endpoint, the packet length and packet data can be read from ISP1161 using the read buffer command. when the whole packet has been read, the ?rmware sends a clear buffer command to enable the reception of new packets. for an in (= transmit) endpoint, the packet length and data to be sent can be written to ISP1161 dc using the write buffer command. when the whole packet has been written to the buffer, the ?rmware sends a validate buffer command to enable data transmission to the host. 11.3.6 special actions on control endpoints control endpoints require special ?rmware actions. the arrival of a setup packet ?ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command to both control endpoints. this ensures that the last setup packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the setup packet.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 48 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 12. dma transfer for the device controller direct memory access (dma) is a method to transfer data from one location to another in a computer system, without intervention of the central processor unit (cpu). many different implementations of dma exist. the ISP1161 dc supports two methods: ? 8237 compatible mode : based on the dma subsystem of the ibm personal computers (pc, at and all its successors and clones); this architecture uses the intel 8237 dma controller and has separate address spaces for memory and i/o ? dack-only mode : based on the dma implementation in some embedded risc processors, which has a single address space for both memory and i/o. the ISP1161 dc supports dma transfer for all 14 con?gurable endpoints (see ta b l e 7 ). only one endpoint at a time can be selected for dma transfer. the dma operation of the ISP1161 dc can be interleaved with normal i/o mode access to other endpoints. the following features are supported: ? single-cycle or burst transfers (up to 16 bytes per cycle) ? programmable transfer direction (read or write) ? multiple end-of-transfer (eot) sources: external pin, internal conditions, short/empty packet ? programmable signal levels on pins dreq2, dack2 and eot. 12.1 selecting an endpoint for dma transfer the target endpoint for dma access is selected via bits epdix[3:0] in the dma con?guration register, as shown in ta b l e 1 0 . the transfer direction (read or write) is automatically set by bit epdir in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). asserting input dack2 automatically selects the endpoint speci?ed in the dma con?guration register, regardless of the current endpoint used for i/o mode access. table 10: endpoint selection for dma transfer endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write 10 1011 out: read in: write
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 49 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 12.2 8237 compatible mode the 8237 compatible dma mode is selected by clearing bit dakoly in the hardware con?guration register (see ta b l e 8 1 ). the pin functions for this mode are shown in ta b l e 1 1 . the dma subsystem of an ibm compatible pc is based on the intel 8237 dma controller. it operates as a ?y-by dma controller: the data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of ISP1161 dc in 8237 compatible dma mode is given in figure 38 . the 8237 has two control signals for each dma channel: dreq (dma request) and d a ck (dma acknowledge). general control signals are hrq (hold request), hlda (hold acknowledge) and eop (end-of-process). the bus operation is controlled via memr (memory read), memw (memory write), ior (i/o read) and io w (i/o write). 11 1100 out: read in: write 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write table 10: endpoint selection for dma transfer continued endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 table 11: 8237 compatible mode: pin functions symbol description i/o function dreq2 dcs dma request o ISP1161 dc requests a dma transfer d a ck2 dcs dma acknowledge i dma controller con?rms the transfer eot end of transfer i dma controller terminates the transfer rd read strobe i instructs ISP1161 dc to put data on the bus wr write strobe i instructs ISP1161 dc to get data from the bus fig 38. ISP1161s device controller in 8237 compatible dma mode. d0 to d15 cpu 004aaa009 ram ISP1161 device controller dma controller 8237 dreq2 dack2 dreq hrq hlda hrq hlda dack ior iow memr memw rd wr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 50 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the following example shows the steps which occur in a typical dma transfer: 1. ISP1161 dc receives a data packet in one of its endpoint fifos; the packet must be transferred to memory address 1234h. 2. ISP1161 dc asserts the dreq2 signal requesting the 8237 for a dma transfer. 3. the 8237 asks the cpu to release the bus by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 now sets its address lines to 1234h and activates the memw and ior control signals. 6. the 8237 asserts d a ck to inform the ISP1161 dc that it will start a dma transfer. 7. the ISP1161 dc now places the word to be transferred on the data bus lines, because its rd signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then de-asserts memw and ior. this latches and stores the word at the desired memory location. it also informs the ISP1161 dc that the data on the bus lines has been transferred. 9. the ISP1161 dc de-asserts the dreq2 signal to indicate to the 8237 that dma is no longer needed. in single cycle mode this is done after each word, in burst mode following the last transferred word of the dma cycle. 10. the 8237 de-asserts the d a ck output indicating that the ISP1161 must stop placing data on the bus. 11. the 8237 places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and de-asserts the hrq signal, informing the cpu that it has released the bus. 12. the cpu acknowledges control of the bus by de-asserting hlda. after activating the bus control lines ( memr, memw, ior and io w) and the address lines, the cpu resumes the execution of instructions. for a typical bulk transfer the above process is repeated, once for each byte. after each byte the address register in the dma controller is incremented and the byte counter is decremented. when using 16-bit dma the number of transfers is 32 and address incrementing and byte counter decrementing is done by 2 for each word. 12.3 dack-only mode the dack-only dma mode is selected by setting bit dakoly in the hardware con?guration register (see ta b l e 8 1 ). the pin functions for this mode are shown in ta b l e 1 2 . a typical example of ISP1161 dc in dack-only dma mode is given in figure 39 . table 12: dack-only mode: pin functions symbol description i/o function dreq2 dcs dma request o ISP1161 dc requests a dma transfer d a ck2 dcs dma acknowledge i dma controller con?rms the transfer; also functions as data strobe
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 51 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. in dack-only mode the ISP1161 dc uses the dack2 signal as a data strobe. input signals rd and wr are ignored. this mode is used in cpu systems that have a single address space for memory and i/o access. such systems have no separate memw and memr signals: the rd and wr signals are also used as memory data strobes. 12.4 end-of-transfer conditions 12.4.1 bulk endpoints a dma transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the dma con?guration register, see ta b l e 8 5 ): ? an external end-of-transfer signal occurs on input eot ? the internal dma counter register reaches zero (cntren = 1) ? a short/empty packet is received on an enabled out endpoint (shortp = 1) ? dma operation is disabled by clearing bit dmaen. external eot: when reading from an out endpoint, an external eot will stop the dma operation and clear any remaining data in the current fifo. for a double- buffered endpoint the other (inactive) buffer is not affected. when writing to an in endpoint, an eot will stop the dma operation and the data packet in the fifo (even if it is smaller than the maximum packet size) will be sent to the usb host at the next in token. dma counter register zero: an eot from the dma counter register is enabled by setting bit cntren in the dma con?guration register. the ISP1161 has a 16-bit dma counter register, which speci?es the number of bytes to be transferred. when eot end-of-transfer i dma controller terminates the transfer rd read strobe i not used wr write strobe i not used fig 39. ISP1161s device controller in dack-only dma mode. table 12: dack-only mode: pin functions continued symbol description i/o function ram ISP1161 device controller dma controller cpu dreq2 dack2 hrq hlda hrq hlda dreq dack rd wr 004aaa010 d0 to d15
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 52 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dma counter register. when the internal counter reaches zero an eot condition is generated and the dma operation stops. short/empty packet: normally, the transfer byte count must be set via a control endpoint before any dma transfer takes place. when a short/empty packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short/empty packet in the data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short/empty packet at an out token will stop the dma operation after transferring the data bytes of this packet. when writing to an in endpoint, a short packet transferred at an in token will stop the dma operation after all bytes have been transferred. if the number of bytes in the buffer is zero, ISP1161 dc will automatically send an empty packet. [1] if short/empty packet eot is enabled (shortp = 1 in dma con?guration register) and dma counter register is zero. 12.4.2 isochronous endpoints a dma transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the dma con?guration register, see ta b l e 8 5 ): ? an external end-of-transfer signal occurs on input eot ? the internal dma counter register reaches zero (cntren = 1) ? an end-of-packet (eop) signal is detected ? dma operation is disabled by clearing bit dmaen. table 13: summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint eot input eot is active eot is active dma counter register counter reaches zero counter reaches zero short packet short packet is received and transferred counter reaches zero in the middle of the buffer empty packet empty packet is received and transferred empty packet is automatically appended when needed [1] dmaen bit in dma con?guration register dmaen = 0 dmaen = 0 table 14: recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint eot input active do not use preferred dma counter register zero do not use preferred end-of-packet preferred do not use
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 53 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13. hc registers the hc contains a set of on-chip control registers. these registers can be read or written by the host controller driver (hcd). the control and status register sets, frame counter register sets, and root hub register sets are grouped under the category of hc operational registers (32 bits). these operational registers are made compatible to openhci (host controller interface) operational registers. this makes a provision that the openhci hcd can be ported to ISP1161 easily. reserved bits may be de?ned in future releases of this speci?cation. to ensure interoperability, the hcd that does not use a reserved ?eld must not assume that the reserved ?eld contains logic 0. furthermore, the hcd must always preserve the values of the reserved ?eld. when a r/w register is modi?ed, the hcd must ?rst read the register, modify the bits desired, and then write the register with the reserved bits still containing the read value. alternatively, the hcd can maintain an in-memory copy of previously written values that can be modi?ed and then written to the hc register. when a write to set or clear the register is written, bits written to reserved ?elds must be logic 0. as shown in ta b l e 1 5 , the offset locations (the commands for reading registers) of these operational registers (the 32-bit registers) are similar to those de?ned in the ohci speci?cation, however, the addresses are equal to offset div 4: table 15: hc control register summary command (hex) register width functionality read write 00 n/a hcrevision 32 hc control and status registers 01 81 hccontrol 32 02 82 hccommandstatus 32 03 83 hcinterruptstatus 32 04 84 hcinterruptenable 32 05 85 hcinterruptdisable 32 0d 8d hcfminterval 32 hc frame counter registers 0e n/a hcfmremaining 32 0f n/a hcfmnumber 32 11 91 hclsthreshold 32 12 92 hcrhdescriptora 32 hc root hub registers 13 93 hcrhdescriptorb 32 14 94 hcrhstatus 32 15 95 hcrhportstatus[1] 32 16 96 hcrhportstatus[2] 32 20 a0 hchardwarecon?guration 16 hc dma and interrupt control registers 21 a1 hcdmacon?guration 16 22 a2 hctransfercounter 16 24 a4 hc m pinterrupt 16 25 a5 hc m pinterruptenable 16
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 54 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.1 hc control and status registers 13.1.1 hcrevision register 27 n/a hcchipid 16 hc miscellaneous registers 28 a8 hcscratch 16 n/a a9 hcsoftwarereset 16 2a aa hcitlbufferlength 16 hc buffer ram control registers 2b ab hcatlbufferlength 16 2c n/a hcbufferstatus 16 2d n/a hcreadbackitl0length 16 2e n/a hcreadbackitl1length 16 40 c0 hcitlbufferport 16 41 c1 hcatlbufferport 16 table 15: hc control register summary continued command (hex) register width functionality read write table 16: hcrevision register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rev reset 10100000- access rrrrrrrr table 17: hcrevision register: bit description bit symbol description 31 to 8 - reserved 7 to 0 rev[7:0] revision: this read-only ?eld contains the bcd representation of the version of the hci speci?cation that is implemented by this hc. for example, a value of 11h corresponds to version 1.1. all hc implementations that are compliant with this speci?cation will have a value of 10h.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 55 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 00 read only 13.1.2 hccontrol register the hccontrol register de?nes the operating modes for the hc. most ?elds are modi?ed only by the hcd, except for hostcontrollerfunctionalstate (hcfs) and remotewakeupconnected (rwc). table 18: hccontrol register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved rwe rwc reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 56 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 01 read code (hex): 81 write 13.1.3 hccommandstatus register the hccommandstatus register is used by the hc to receive commands issued by the hcd, and it also re?ects the hcs current status. to the hcd, it appears to be a write to set register. the hc must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the hc without concern for corrupting previously issued commands. the hcd has normal read access to all bits. table 19: hccontrol register: bit description bit symbol description 31 to 11 - reserved 10 rwe remotewakeupenable: this bit is used by the hcd to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. when this bit is set and the resumedetected bit in hcinterruptstatus is set, a remote wakeup is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remotewakeupconnected: this bit indicates whether the hc supports remote wakeup signaling. if remote wakeup is supported and used by the system, it is the responsibility of system ?rmware to set this bit during post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wakeup signaling of the host system is host-bus-speci?c and is not described in this speci?cation. 8 - reserved 7 to 6 hcfs hostcontrollerfunctionalstate for usb: 00b usbreset 01b usbresume 10b usboperational 11b usbsuspend a transition to usboperational from another state causes start-of-frame (sof) generation to begin 1 ms later. the hcd may determine whether the hc has begun sending sofs by reading the startofframe ?eld of hcinterruptstatus. this ?eld may be changed by the hc only when in the usbsuspend state. the hc may move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the hc enters usbsuspend after a software reset; it enters usbreset after a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 to 0 - reserved
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 57 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the schedulingoverruncount ?eld indicates the number of frames with which the hc has detected the scheduling overrun error. this occurs when the periodic list does not complete before eof. when a scheduling overrun error is detected, the hc increments the counter and sets the schedulingoverrun ?eld in the hcinterruptstatus register. code (hex): 02 read code (hex): 82 write table 20: hccommandstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol reserved soc[1:0] reset 00000000 access rr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved hcr reset 00000000 access r/w table 21: hccommandstatus register: bit description bit symbol description 31 to 18 - reserved 17 to 16 soc[1:0] schedulingoverruncount: the ?eld is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it will be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by hcd to monitor any persistent scheduling problems. 15 to 1 - reserved 0 hcr hostcontrollerreset: this bit is set by hcd to initiate a software reset of hc. regardless of the functional state of hc, it moves to the usbsuspend state in which most of the operational registers are reset except those stated otherwise; e.g., the interruptrouting ?eld of hccontrol, and no host bus accesses are allowed. this bit is cleared by hc upon the completion of the reset operation. the reset operation must be completed within 10 s. this bit, when set, should not cause a reset to the root hub and no subsequent reset signaling should be asserted to its downstream ports.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 58 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.1.4 hcinterruptstatus register this register provides the status of the events that cause hardware interrupts. when an event occurs, the hc sets the corresponding bit in this register. when a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register (see section 13.1.5 ) and the masterinterruptenable bit is set. the hcd may clear speci?c bits in this register by writing logic1 to the bit positions to be cleared. the hcd may not set any of these bits. the hc will not clear the bit. table 22: hcinteruptstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 59 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 03 read code (hex): 83 write 13.1.5 hcinterruptenable register each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. when these three conditions occur: ? a bit is set in the hcinterruptstatus register ? the corresponding bit in the hcinterruptenable register is set ? the masterinterruptenable bit is set ? then a hardware interrupt is requested on the host bus. writing a logic1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. table 23: hcinterruptstatus register: bit description bit symbol description 31 to 8 reserved 7 reserved - 6 rhsc roothubstatuschange: this bit is set when the content of hcrhstatus or the content of any of hcrhportstatus[numberofdownstreamport] has changed. 5 fno framenumberover?ow: this bit is set when the msb of hcfmnumber (bit 15) changes value, from logic 0 to 1 or from logic 1 to 0. 4ue unrecoverableerror: this bit is set when the hc detects a system error not related to usb. the hc should not proceed with any processing nor signaling before the system error has been corrected. the hcd clears this bit after hc has been reset. phci: always set to logic 0. 3rd resumedetected: this bit is set when the hc detects that a device on the usb is asserting resume signaling. it is the transition from no resume signaling to resume signaling causing this bit to be set. this bit is not set when hcd sets the usbresume state. 2sf startofframe: at the start of each frame, this bit is set by the hc and an sof generated. 1 - reserved 0so schedulingoverrun: this bit is set when usb schedules for current frame overruns. a scheduling overrun will also cause the schedulingoverruncount of hccommandstatus to be incremented.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 60 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 04 read code (hex): 84 write table 24: hcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w table 25: hcinterruptenable register: bit description bit symbol description 31 mie masterinterruptenable by the hcd: a logic 0 is ignored by the hc. a logic 1 enables interrupt generation by events speci?ed in other bits of this register. 30 to 8 - reserved 7 - reserved 6 rhsc 0 ignore 1 enable interrupt generation due to root hub status change 5 fno 0 ignore 1 enable interrupt generation due to frame number over?ow 4ue 0 ignore 1 enable interrupt generation due to unrecoverable error 3rd 0 ignore 1 enable interrupt generation due to resume detect 2sf 0 ignore 1 enable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 enable interrupt generation due to scheduling overrun
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 61 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.1.6 hcinterruptdisable register each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing a logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing a logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. table 26: hcinterruptdisable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 00000000 access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset 00000000 access r/w table 27: hcinterruptdisable register: bit description bit symbol description 31 mie a logic 0 is ignored by the hc. a logic 1 disables interrupt generation due to events speci?ed in other bits of this register. this ?eld is set after a hardware or software reset. 30 to 8 - reserved 7 - reserved 6 rhsc 0 ignore 1 disable interrupt generation due to root hub status change
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 62 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 05 read code (hex): 85 write 13.2 hc frame counter registers 13.2.1 hcfminterval register the hcfminterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive sofs), and a 15-bit value indicating the full-speed maximum packet size that the hc may transmit or receive without causing a scheduling overrun. the hcd may carry out minor adjustments on the frameinterval by writing a new value over the present one at each sof. this provides the programmability necessary for the hc to synchronize with an external clocking resource and to adjust any unknown local clock offset. 5 fno 0 ignore 1 disable interrupt generation due to frame number over?ow 4ue 0 ignore 1 disable interrupt generation due to unrecoverable error 3rd 0 ignore 1 disable interrupt generation due to resume detect 2sf 0 ignore 1 disable interrupt generation due to start of frame 1 - reserved 0so 0 ignore 1 disable interrupt generation due to scheduling overrun table 27: hcinterruptdisable register: bit description continued bit symbol description table 28: hcfminterval register: bit allocation bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00000000 access r/w bit 15 14 13 12 11 10 9 8 symbol reserved fi[13:8] reset 00101110 access r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset 11011111 access r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 63 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 0d read code (hex): 8d write 13.2.2 hcfmremaining register the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. table 29: hcfminterval register: bit description bit symbol description 31 fit frameintervaltoggle: the hcd toggles this bit whenever it loads a new value to frameinterval. 30 to 16 fsmps [14:0] fslargestdatapacket: speci?es a value which is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits which can be sent or received by the hc in a single transaction at any given time without causing a scheduling overrun. the ?eld value is calculated by the hcd. 15 to 14 - reserved 13 to 0 fi[13:0] frameinterval: speci?es the interval between two consecutive sofs in bit times. the nominal value is set to be 11999. the hcd must store the current value of this ?eld before resetting the hc. by setting the hostcontrollerreset bit 0 ?eld of hccommandstatus register will cause the hc to reset this ?eld to its nominal value. hcd may choose to restore the stored value upon completing the reset sequence. table 30: hcfmremaining register: bit allocation bit 31 30 29 28 27 26 25 24 symbol frt reserved reset 00000000 access rr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r bit 15 14 13 12 11 10 9 8 symbol reserved fr[13:8] reset 00000000 access rr bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00000000 access r
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 64 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 0e read 13.2.3 hcfmnumber register the hcfmnumber register is a 16-bit counter. it provides a timing reference for events happening in the hc and the hcd. the hcd may use the 16-bit value speci?ed in this register and generate a 32-bit frame number without requiring frequent access to the register. table 31: hcfmremaining register: bit description bit symbol description 31 frt frameremainingtoggle: this bit is loaded from the frameintervaltoggle ?eld of hcfminterval whenever frameremaining reaches 0. this bit is used by the host controller driver (hcd) for synchronization between frameinterval and frameremaining. 30 to 14 - reserved 13 to 0 fr[13:0] frameremaining: this counter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterval value speci?ed in hcfminterval at the next bit time boundary. when entering the usboperational state, the hc reloads it with the content of the frameinterval part of the hcfminterval register and uses the updated value from the next sof. table 32: hcfmnumber register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r bit 15 14 13 12 11 10 9 8 symbol fn[15:8] reset 00000000 access r bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00000000 access r
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 65 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 0f read 13.2.4 hclsthreshold register the hclsthreshold register contains an 11-bit value used by the hc to determine whether to commit to the transfer of a maximum of 8-byte ls packet before eof. neither the hc nor the hcd is allowed to change this value. table 33: hcfmnumber register: bit description bit symbol description 31 to 16 - reserved 15 to 0 fn[15:0] framenumber: this is incremented when hcfmremaining is reloaded. it will be rolled over to 0h after ffffh. when the usboperational state is entered, this will be incremented automatically. hc will set the startofframe in hcinterruptstatus. table 34: hclsthreshold register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved lst[10:8] reset 0 0000110 access r/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 00101000 access r/w table 35: hclsthreshold register: bit description bit symbol description 31 to 16 - reserved 15 to 11 - reserved 10 to 0 lst[10:0] lsthreshold: contains a value that is compared to the frameremaining ?eld before a low-speed transaction is initiated. the transaction is started only if frameremaining 3 this ?eld. the value is calculated by the hcd, which considers transmission and setup overhead.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 66 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 11 read code (hex): 91 write 13.3 hc root hub registers all registers included in this partition are dedicated to the usb root hub, which is an integral part of the hc although it is a functionally separate entity. the host controller driver (hcd) emulates usbd accesses to the root hub via a register interface. the hcd maintains many usb-de?ned hub features that are not required to be supported in hardware. for example, the hubs device, con?guration, interface, and endpoint descriptors are maintained only in the hcd as well as some static ?elds of the class descriptor. the hcd also maintains and decodes the root hubs device address as well as other trivial operations that they are better suited to software than to hardware. the root hub registers are developed to maintain the similarity of bit organization and operation to typical hubs found in the system. four registers are de?ned as follows: ? hcrhdescriptora ? hcrhdescriptorb ? hcrhstatus ? hcrhportstatus[1:ndp] each register is read and written as a dword. these registers are only written during initialization to correspond with the system implementation. the hcrhdescriptora and hcrhdescriptorb registers should be implemented such that they are writeable regardless of the hcs usb states. hcrhstatus and hcrhportstatus must be writeable during the usboperational state. 13.3.1 hcrhdescriptora register the hcrhdescriptora register is the ?rst register of two describing the characteristics of the root hub. reset values are implementation-speci?c (is). the descriptor length (11), descriptor type and hub controller current (0) ?elds of the hub class descriptor are emulated by the hcd. all other ?elds are located in the registers hcrhdescriptora and hcrhdescriptorb. remark: is denotes an implementation-speci?c reset value for that ?eld.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 67 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. table 36: hcrhdescriptora register: bit description bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset is access r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset 00h access r/w bit 15 14 13 12 11 10 9 8 symbol reserved nocp ocpm dt nps psm reset 0 0 0 is is 0 is is access r/w r/w r/w r r/w r/w bit 7 6 5 4 3 2 1 0 symbol ndp[7:0] reset is access r
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 68 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 12 read code (hex): 92 write table 37: hcrhdescriptora register: bit description bit symbol description 31 to 24 potpgt [7:0] powerontopowergoodtime: this byte speci?es the duration hcd has to wait before accessing a powered-on port of the root hub. it is implementation-speci?c (is). the unit of time is 2 ms. the duration is calculated as potpgt 2 ms. 23 to 13 - reserved 12 nocp noovercurrentprotection: this bit describes how the overcurrent status for the root hub ports are reported. when this bit is cleared, the overcurrentprotectionmode ?eld speci?es global or per-port reporting. 0 overcurrent status is reported collectively for all downstream ports 1 no overcurrent protection supported 11 ocpm overcurrentprotectionmode: this bit describes how the overcurrent status for the root hub ports is reported. at reset, this ?eld should re?ect the same mode as powerswitchingmode. this ?eld is valid only if the noovercurrentprotection ?eld is cleared. 0 overcurrent status is reported collectively for all downstream ports 1 overcurrent status is reported on a per-port basis 10 dt devicetype: this bit speci?es that the root hub is not a compound deviceit is not permitted. this ?eld should always read/write 0. 9 nps nopowerswitching: these bits are used to specify whether power switching is supported or ports are always powered. it is implementation-speci?c. when this bit is cleared, the bit powerswitchingmode speci?es global or per-port switching. 0 ports are power switched 1 ports are always powered on when the hc is powered on 8 psm powerswitchingmode: this bit is used to specify how the power switching of the root hub ports is controlled. it is implementation-speci?c. this ?eld is valid only if the nopowerswitching ?eld is cleared. 0 all ports are powered at the same time 1 each port is powered individually. this mode allows port power to be controlled by either the global switch or per-port switching. if the bit portpowercontrolmask is set, the port responds to only port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7 to 0 ndp[7:0] numberdownstreamports: these bits specify the number of downstream ports supported by the root hub. it is implementation-speci?c. the minimum number of ports is 1. the maximum number of ports supported by openhci is 2.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 69 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.3.2 hcrhdescriptorb register the hcrhdescriptorb register is the second register of two describing the characteristics of the root hub. these ?elds are written during initialization to correspond with the system implementation. reset values are implementation-speci?c (is). table 38: hcrhdescriptorb register: bit allocation bit 31 30 29 28 27 26 25 24 symbol ppcm[15:8] reset is access r/w bit 23 22 21 20 19 18 17 16 symbol ppcm[7:0] reset is access r/w bit 15 14 13 12 11 10 9 8 symbol dr[15:8] reset is access r/w bit 7 6 5 4 3 2 1 0 symbol dr[7:0] reset is access r/w table 39: hcrhdescriptorb register: bit description bit symbol description 31 to 16 ppcm [15:0] portpowercontrolmask: each bit indicates whether a port is affected by a global power control command when powerswitchingmode is set. when set, the ports power state is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is con?gured to global switching mode (powerswitchingmode = 0), this ?eld is not valid. bit 0 reserved bit 1 ganged-power mask on port #1 bit 2 ganged-power mask on port #2 ... bit 15 ganged-power mask on port #15 15 to 0 dr [15:0] deviceremovable: each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0 reserved bit 1 device attached to port #1 bit 2 device attached to port #2 ... bit 15 device attached to port #15
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 70 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 13 read code (hex): 93 write 13.3.3 hcrhstatus register the hcrhstatus register is divided into two parts. the lower word of a dword represents the hub status ?eld and the upper word represents the hub status change ?eld. reserved bits should always be written as logic 0. table 40: hcrhstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol crwe reserved reset n/a n/a access w n/a bit 23 22 21 20 19 18 17 16 symbol reserved ccic lpsc reset n/a 0 0 access n/a r/w r/w bit 15 14 13 12 11 10 9 8 symbol drwe reserved reset 00000000 access r/w - bit 7 6 5 4 3 2 1 0 symbol reserved oci lps reset 00000000 access n/a r r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 71 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 14 read code (hex): 94 write table 41: hcrhstatus register: bit description bit symbol description 31 crwe on write clearremotewakeupenable: writing a logic 1 clears deviceremovewakeupenable. writing a logic 0 has no effect. 30 to 18 - reserved 17 ccic overcurrentindicatorchange: this bit is set by hardware when a change has occurred to the oci ?eld of this register. the hcd clears this bit by writing a logic 1. writing a logic 0 has no effect. 16 lpsc on read localpowerstatuschange: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write setglobalpower: in global power mode (powerswitchingmode=0), this bit is written to logic 1 to turn on power to all ports (clear portpowerstatus). in per-port power mode, it sets portpowerstatus only on ports whose bit portpowercontrolmask is not set. writing a logic 0 has no effect. 15 drwe on read deviceremotewakeupenable: this bit enables the bit connectstatuschange as a resume event, causing a state transition usbsuspend to usbresume and setting the resumedetected interrupt. 0 connectstatuschange is not a remote wakeup event 1 connectstatuschange is a remote wakeup event on write setremotewakeupenable: writing a logic 1 sets deviceremovewakeupenable. writing a logic 0 has no effect. 14 to 2 - reserved 1 oci overcurrentindicator: this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when clear, all power operations are normal. if per-port overcurrent protection is implemented this bit is always logic 0. 0 lps on read localpowerstatus: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clearglobalpower: in global power mode (powerswitchingmode = 0), this bit is written to logic 1 to turn off power to all ports (clear portpowerstatus). in per-port power mode, it clears portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing a logic 0 has no effect.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 72 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.3.4 hcrhportstatus[1:2] the hcrhportstatus[1:2] register is used to control and report port events on a per-port basis. numberdownstreamports represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to re?ect the port status, whereas the upper word re?ects the status change bits. some status bits are implemented with special write behavior. if a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written logic 0. table 42: hcrhportstatus[1:2] register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00h access r/w bit 23 22 21 20 19 18 17 16 symbol reserved prsc ocic pssc pesc csc reset 00000000 access r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lsda pps reset n/a x 0 access n/a r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved prs poci pss pes ccs reset 00000000 access r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 73 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. table 43: hcrhportstatus[1:2] register: bit description bit symbol description 31 to 21 - reserved 20 prsc portresetstatuschange: this bit is set at the end of the 10 ms port reset signal. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 port reset is not complete 1 port reset is complete 19 ocic portovercurrentindicatorchange: this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when root hub changes the portovercurrentindicator bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portovercurrentindicator 1 portovercurrentindicator has changed 18 pssc portsuspendstatuschange: this bit is set when the full resume sequence has been completed. this sequence includes the 20 s resume pulse, ls eop, and 3 ms re-synchronization delay. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. this bit is also cleared when resetstatuschange is set. 0 resume is not completed 1 resume is completed 17 pesc portenablestatuschange: this bit is set when hardware events cause the portenablestatus bit to be cleared. changes from hcd writes do not set this bit. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. 0 no change in portenablestatus 1 change in portenablestatus 16 csc connectstatuschange: this bit is set whenever a connect or disconnect event occurs. the hcd writes a logic 1 to clear this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared when a setportreset, setportenable, or setportsuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0 no change in currentconnectstatus 1 change in currentconnectstatus remark: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 - reserved 9 lsda (read) lowspeeddeviceattached: this bit indicates the speed of the device attached to this port. when set, a low-speed device is attached to this port. when clear, a full-speed device is attached to this port. this ?eld is valid only when the currentconnectstatus is set. 0 full-speed device attached 1 low-speed device attached (write) clearportpower: the hcd clears the portpowerstatus bit by writing a logic 1 to this bit. writing a logic 0 has no effect.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 74 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 8 pps (read) portpowerstatus: this bit re?ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd sets this bit by writing setportpower or setglobalpower. the hcd clears this bit by writing clearportpower or clearglobalpower. which power control switches are enabled is determined by powerswitchingmode. in the global switching mode (powerswitchingmode = 0), only set/clearglobalpower controls this bit. in per-port power switching (powerswitchingmode = 1), if the portpowercontrolmask[ndp] bit for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnectstatus, portenablestatus, portsuspendstatus, and portresetstatus should be reset. 0 port power is off 1 port power is on (write) setportpower: the hcd writes a logic 1 to set the portpowerstatus bit. writing a logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved 4 prs (read) portresetstatus: when this bit is set by a write to setportreset, port reset signaling is asserted. when reset is completed, this bit is cleared when portresetstatuschange is set. this bit cannot be set if currentconnectstatus is cleared. 0 port reset signal is not active 1 port reset signal is active (write) setportreset: the hcd sets the port reset signaling by writing a 1 to this bit. writing a 0 has no effect. if currentconnectstatus is cleared, this write does not set portresetstatus but instead sets connectstatuschange. this informs the driver that it attempted to reset a disconnected port. 3 poci (read) portovercurrentindicator: this bit is valid only when the root hub is con?gured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always re?ects the overcurrent input signal 0 no overcurrent condition 1 overcurrent condition detected (write) clearsuspendstatus: the hcd writes a logic 1 to initiate a resume. writing a logic 0 has no effect. a resume is initiated only if portsuspendstatus is set. table 43: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 75 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): [1] = 15, [2] = 16 read code (hex): [1] = 95, [2] = 96 write 2 pss (read) portsuspendstatus: this bit indicates whether the port is suspended or in the resume sequence. it is set by a setsuspendstate write and cleared when portsuspendstatuschange is set at the end of the resume interval. this bit cannot be set if currentconnectstatus is cleared. this bit is also cleared when portresetstatuschange is set at the end of the port reset or when the hc is placed in the usbresume state. if an upstream resume is in progress, it should propagate to the hc. 0 port is not suspended 1 port is suspended (write) setportsuspend: the hcd sets the portsuspendstatus bit by writing a logic 1 to this bit. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portsuspendstatus; instead it sets connectstatuschange. this informs the driver that it attempted to suspend a disconnected port. 1 pes (read) portenablestatus: this bit indicates whether the port is enabled or disabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. this change also causes portenabledstatuschange to be set. the hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus is cleared. this bit is also set, if it is not already, at the completion of a port reset when resetstatuschange is set or port suspend when suspendstatuschange is set. 0 port is disabled 1 port is enabled (write) setportenable: the hcd sets portenablestatus by writing a logic 1. writing a logic 0 has no effect. if currentconnectstatus is cleared, this write does not set portenablestatus, but instead sets connectstatuschange. this informs the driver that it attempted to enable a disconnected port. 0 ccs (read) currentconnectstatus: this bit re?ects the current state of the downstream port. 0 no device connected 1 device connected (write) clearportenable: the hcd writes a logic 1 to this bit to clear the portenablestatus bit. writing a logic 0 has no effect. currentconnectstatus is not affected by any write. remark: this bit always reads logic 1 when the attached device is nonremovable (deviceremoveable[ndp]). table 43: hcrhportstatus[1:2] register: bit description continued bit symbol description
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 76 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.4 hc dma and interrupt control registers 13.4.1 hchardwarecon?guration register table 44: hchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved 2_down streamport 15k resistorsel suspend clknotstop analogoc enable reserved dackmode reset 00000 000 access r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol eotinput polarity dackinput polarity dreqout putpolarity databuswidth interruptout putpolarity interruptpi ntrigger interruptpin enable reset 00001 000 access r/w r/w r/w r/w r/w r/w r/w table 45: hchardwarecon?guration register: bit description bit symbol description 15 to 13 - reserved 12 2_downstreamport15kresistorsel 0 use external 15 k w resistors for downstream ports 1 use built-in resistors for downstream ports 11 suspendclknotstop 0 clk can be stopped 1 clock can not be stopped 10 analogocenable 0 use external oc detection. digital input 1 use on-chip oc detection. analog input 9 - reserved 8 dackmode 0 normal operation. dack1 is used with read and write signals. power-up value. 1 reserved 7 eotinputpolarity 0 active low. power-up value 1 active high 6 dackinputpolarity 0 active low. power-up value 1 active high 5 dreqoutputpolarity 0 active low 1 active high. power-up value 4 to 3 databuswidth[1:0] 01 16 bits others reserved 2 interruptoutputpolarity 0 active low. power-up value 1 active high 1 interruptpintrigger 0 interrupt is level-triggered. power-up value 1 interrupt is edge-triggered. 0 interruptpinenable 0 power-up value 1 pin global interrupt int1 is enabled
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 77 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 20 read code (hex): a0 write remark: 1. bit 0, interruptpinenable, is used as pin int1s master interrupt enable. this bit should be used together with the register hc m pinterruptenable to enable pin int1. 2. bits 4:3 are ?xed at the value 01b for ISP1161. 13.4.2 hcdmacon?guration register code (hex): 21 read code (hex): a1 write table 46: hcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved burstlen[1:0] dma enable reserved dmacount erselect itl_atl_ dataselect dmaread writeselect reset 00000000 access r/w r/w r/w r/w r/w r/w r/w table 47: hcdmacon?guration register: bit description bit symbol description 15 to 8 - reserved 7 - reserved 6 to 5 burstlen[1:0] 00b single-cycle burst dma 01b 4-cycle burst dma 10b 8-cycle burst dma 11b reserved 4 dmaenable 0 dma is terminated 1 dma is enabled this bit will be reset to zero when dma transfer is completed 3 - reserved 2 dmacounter select 0 dma counter not used. external eot must be used 1 enables the dma counter for dma transfer. hctransfercounter register must be ?lled with non-zero values for dreq1 to be raised after bit dma enable is set 1 itl_atl_ dataselect 0 itl buffer ram selected for itl data 1 atl buffer ram selected for atl data 0 dmaread writeselect 0 read from ISP1161 hcs fifo buffer ram 1 write to ISP1161 hcs fifo buffer ram
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 78 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.4.3 hctransfercounter register this register holds the number of bytes of a pio or dma transfer. for a pio transfer, the number of bytes being read or written to the (isochronous transfer list) itl or (acknowledged transfer list) atl buffer ram must be written into this register. for a dma transfer, the number of bytes must be written into this register as well. however, for this counter to be read into the dma counter, the hcd must set bit 2 of the hcdmacon?guration register. the counter value for atl must not be greater than 1000h, and for itl it must not be greater than 800h. when the byte count of the data transfer reaches this value, the hc will generate an internal eot signal to set bit 2 alleointerrupt, of the hc m pinterrupt register, and also update the hcbufferstatus register. code (hex): 22 read code (hex): a2 write 13.4.4 hc m pinterrupt register all the bits in this register will be active on power-on reset. however, none of the active bits will cause an interrupt on the interrupt pin (int1) unless they are set by the respective bits in the hc m pinterruptenable register, and together with bit 0 of the hchardwarecon?guration register. after this register (24h read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (a4h - write) to clear it. the bits in this register are cleared only when you write to this register indicating the bits to be cleared. to clear all the enabled bits in this register, the hcd must write ffh to this register. table 48: hctransfercounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol counter value reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol counter value reset 00000000 access r/w table 49: hctransfercounter register: bit description bit symbol description 15 to 0 counter value the number of data bytes to be read to or written from ram
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 79 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 24 read code (hex): a4 write table 50: hc m pinterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended opr_reg reserved alleot interrupt atlint sofitlint reset 00000000 access r/w table 51: hc m pinterrupt register: bit description bit symbol description 15 to 8 - reserved 7 - reserved 6 clkready 0 no event 1 clock is ready. (after a wakeup is sent, there is a wait for clock ready. maximum is 1 ms, and typical is 160 m s) 5 hcsuspen ded 0 no event 1 the hc has been suspended and no usb activity is sent from the microprocessor for each ms. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr_reg read hccontrol and hcinterrupt registers to detect type of interrupt on the hc (if the hc requires the operational register to be updated) 3 - reserved 2 alleotinter rupt 0 no event 1 implies that data transfer has been ?nished via pio transfer or dma transfer. occurrence of internal or external eot will set this bit. 1 atlint 0 no event 1 implies that the microprocessor must read atl data from the hc. this requires that the hcbufferstatus register must ?rst be read. the time for this interrupt depends on the number of clocks bit set for usb activities in each ms. 0 sofitlint 0 no event 1 implies that sof indicates the 1 ms mark. the itl buffer that the hc has handled must be read. to know the itl buffer status, the hcbufferstatus register must ?rst be read. this is for microprocessor to get iso data to or from the hc. for more information, see section 9.5 on page 33 6th paragraph.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 80 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 13.4.5 hcupinterruptenable register the bits 6:0 in this register are the same as those in the hc m pinterrupt register. they are used together with bit 0 of the hchardwarecon?guration register to enable or disable the bits in the hc m pinterrupt register. on power-on, all bits in this register are masked with 0. this means no interrupt request output on the interrupt pin int1 can be generated. when the bit is set to 1, the interrupt for the bit is not masked but enabled. table 52: hc m pinterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r/w bit 7 6 5 4 3 2 1 0 symbol reserved clkready hc suspended enable opr interrupt enable reserved eot interrupt enable at l interrupt enable sof interrupt enable reset 00000000 access r/w table 53: hc m pinterruptenable register: bit description bit symbol description 15 to 8 - reserved 7 - reserved 6 clkready 0 power-up value 1 enables clkready interrupt 5hc suspended enable 0 power-up value 1 enables hc suspended interrupt. when the microprocessor wants to suspend the hc, the microprocessor must write to the hccontrol register. and when all downstream devices are suspended, then the hc stops sending sof; the hc is suspended by having the hccontrol register written into. 4 opr interrupt enable 0 power-up value 1 enables the 32-bit operational registers interrupt (if the hc requires the operational register to be updated) 3 - reserved 2eot interrupt enable 0 power-up value 1 enables the eot interrupt which indicates an end of a read/write transfer 1atl interrupt enable 0 power-up value 1 enables atl interrupt. the time for this interrupt depends on the number of clock bits set for usb activities in each ms. 0 sof interrupt enable 0 power-up value 1 enables the interrupt bit due to sof (for the microprocessor dma to get iso data from the hc by ?rst accessing the hcdmacon?guration register)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 81 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 25 read code (hex): a5 write 13.5 hc miscellaneous registers 13.5.1 hcchipid register read this register to get the id of the ISP1161 silicon chip. the high byte stands for the product name (here 61h stands for ISP1161). the low byte indicates the revision number of the product including engineering samples (here 10h means revision 1, that is es1 of ISP1161). code (hex): 27 read 13.5.2 hcscratch register this register is for the hcd to save and restore values when required. code (hex): 28 read table 54: hcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipid[15:8] reset 01100001 access r bit 7 6 5 4 3 2 1 0 symbol chipid[7:0] reset 00000000 access r table 55: hcchipid register: bit description bit symbol description 15 to 0 chipid [15:0] ISP1161s chip id table 56: hcscratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol scratch[15:8] reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol scratch[7:0] reset 00000000 access r/w table 57: hcscratch register: bit description bit symbol description 15 to 0 scratch [15:0] scratch register value
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 82 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): a8 write 13.5.3 hcsoftwarereset register this is a soft reset command. the microprocessor writes a9h to ISP1161s command port, resetting all the hcs internal registers except for the internal fifo buffer ram. code (hex): a9 write 13.6 hc buffer ram control registers 13.6.1 hcitlbufferlength register write to this register to assign the itl buffer size in bytes for both itl0 and itl1 simultaneously. thus, the itl0 and itl1 always have the same size. must follow the formula: atl buffer length + 2 (itl buffer size) 1000h (that is, 4 kbytes) where: itl buffer size = itl0 buffer length = itl1 buffer length table 58: hcsoftwarereset register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reset[15:8] reset xxxxxxxx access w bit 7 6 5 4 3 2 1 0 symbol reset[7:0] reset 11110110 access w table 59: hcsoftwarereset register: bit description bit symbol description 15 to 0 reset[15:0] soft reset command table 60: hcitlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol itlbufferlength[15:8] reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol itlbufferlength[7:0] reset 00000000 access r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 83 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 2a read code (hex): aa write 13.6.2 hcatlbufferlength register write to this register to assign atl buffer size. code (hex): 2b read code (hex): ab write remark: the maximum total ram size is 1000h (4096 in decimal) bytes. that means itl0 (length) + itl1 (length) + atl (length) 1000h bytes. for example: if atl buffer length has been set to be 800h, then the maximum itl buffer length can only be set as 400h. 13.6.3 hcbufferstatus register table 61: hcitlbufferlength register: bit description bit symbol description 15 to 0 itlbufferlength [15:0] assign itl buffer length table 62: hcatlbufferlength register: bit allocation bit 15 14 13 12 11 10 9 8 symbol atlbufferlength[15:8] reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol atlbufferlength[7:0] reset 00000000 access r/w table 63: hcatlbufferlength register: bit description bit symbol description 15 to 0 atlbufferlength [15:0] assign atl buffer length table 64: hcbufferstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00h access r bit 7 6 5 4 3 2 1 0 symbol reserved atlbuffer done itl1buffer done itl0buffer done atlbuffer full itl1buffer full itl0buffer full reset 00000000 access r rrrrrr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 84 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 2c read 13.6.4 hcreadbackitl0length register this registers value stands for the current number of data bytes inside an itl0 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl0 buffer ram. code (hex): 2d read 13.6.5 hcreadbackitl1length register this registers value stands for the current number of data bytes inside the itl1 buffer to be read back by the microprocessor. the hcd must set the hctransfercounter equivalent to this value before reading back the itl1 buffer ram. table 65: hcbufferstatus register: bit description bit symbol description 15 to 8 - reserved 7 to 6 - reserved 5 atlbuffer done 0 atl buffer not read by hc yet 1 atl buffer read by hc 4 itl1buffer done 0 itl1 buffer not read by hc yet 1 itl1 buffer read by hc 3 itl0buffer done 0 1tl0 buffer not read by hc yet 1 1tl0 buffer read by hc 2 atlbuffer full 0 atl buffer is empty 1 atl buffer is full 1 itl1buffer full 0 1tl1 buffer is empty 1 1tl1 buffer is full 0 itl0buffer full 0 itl0 buffer is empty 1 itl0 buffer is full table 66: hcreadbackitl0length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl0bufferlength[15:8] reset 00000000 access r bit 7 6 5 4 3 2 1 0 symbol rditl0bufferlength[7:0] reset 00000000 access r table 67: hcreadbackitl0length register: bit description bit symbol description 15 to 0 rditl0bufferlength [15:0] the number of bytes for itl0 data to be read back by the microprocessor
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 85 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. code (hex): 2e read 13.6.6 hcitlbufferport register this is the itl buffer ram read/write port. the bits 15:8 contain the data byte that comes from the itl buffer rams even address. the bits 7:0 contain the data byte that comes from the itl buffer rams odd address. code (hex): 40 read code (hex): c0 write the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (40h for read, c0h for write) once only, and then read or write all the data bytes in word. after every read/write, the pointer of itl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of hctransfercounter register; otherwise, an internal eot signal is not generated to set the bit 2 alleotinterrupt, of the hc m pinterrupt register and update the hcbufferstatus register. table 68: hcreadbackitl1length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol rditl1bufferlength[15:8] reset 00000000 access r bit 7 6 5 4 3 2 1 0 symbol rditl1bufferlength[7:0] reset 00000000 access r table 69: hcreadbackitl1length register: bit description bit symbol description 15 to 0 rditl1bufferlength [15:0] the number of bytes for itl1 data to be read back by the microprocessor table 70: hcitlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00000000 access r/w table 71: hcitlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write itl buffer rams two data bytes.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 86 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the hcd must take care of the difference that the internal buffer ram is organized in bytes. the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 word). 13.6.7 hcatlbufferport register this is the atl buffer ram read/write port. the bits 15:8 contain the data byte that comes from the acknowledged transfer list (atl) buffer rams even address. the bits 7:0 contain the data byte that comes from the atl buffer rams odd address. code (hex): 41 read code (hex): c1 write the hcd must set the byte count into the hctransfercounter register and check the hcbufferstatus register before reading from or writing to the buffer. the hcd must write the command (41h for read, c1h for write) once only, and then read or write all the data bytes in word. after every read/write, the pointer of atl buffer ram will be automatically increased by two to point to the next data word until it reaches the value of hctransfercounter register; otherwise, an internal eot signal is not generated to set the bit 2 alleotinterrupt, of the hc m pinterrupt register and update the hcbufferstatus register. the hcd must take care of the difference: the internal buffer ram is organized in bytes, so the hcd must write the byte count into the hctransfercounter register, but the hcd reads or writes the buffer ram by 16 bits (by 1 word). 14. dc commands and registers the functions and registers of ISP1161 are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in ta b l e 7 4 . a complete access consists of two phases: table 72: hcatlbufferport register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataword[15:8] reset 00000000 access r/w bit 7 6 5 4 3 2 1 0 symbol dataword[7:0] reset 00000000 access r/w table 73: hcatlbufferport register: bit description bit symbol description 15 to 0 dataword[15:0] read/write atl buffer rams two data bytes.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 87 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 1. command phase : when address bit a0 = 1, the dc interprets the data on the lower byte of the bus (bits d7 to d0) as a command code. commands without a data phase are executed immediately. 2. data phase (optional) : when address bit a0 = 0, the dc transfers the data on the bus to or from a register or endpoint fifo. multi-byte registers are accessed least signi?cant byte/word ?rst. as the ISP1161 dcs data bus is 16 bits wide: ? the upper byte (bits d15 to d8) in command phase or the unde?ned byte in data phase is ignored. ? the access of registers is word-aligned: byte access is not allowed. ? if the packet length is odd, the upper byte of the last word in an in endpoint buffer is not transmitted to the host. when reading from an out endpoint buffer, the upper byte of the last word must be ignored by the ?rmware. the packet length is stored in the ?rst 2 bytes of the endpoint buffer. table 74: command and register summary name destination code (hex) transaction [1] initialization commands write control out con?guration endpoint con?guration register endpoint 0 out 20 write 1 word write control in con?guration endpoint con?guration register endpoint 0 in 21 write 1 word write endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoint 1 to 14 22 to 2f write 1 word read control out con?guration endpoint con?guration register endpoint 0 out 30 read 1 word read control in con?guration endpoint con?guration register endpoint 0 in 31 read 1 word read endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoint 1 to 14 32 to 3f read 1 word write/read device address address register b6/b7 write/read 1 word write/read mode register mode register b8/b9 write/read 1 word write/read hardware con?guration hardware con?guration register ba/bb write/read 1 word write/read interrupt enable register interrupt enable register c2/c3 write/read 2 words write/read dma con?guration dma con?guration register f0/f1 write/read 1 word write/read dma counter dma counter register f2/f3 write/read 1 word reset device resets all registers f6 - data ?ow commands write control out buffer illegal: endpoint is read-only (00) - write control in buffer fifo endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt/bulk: n 64 bytes read control out buffer fifo endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) -
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 88 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. read endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes [6] interrupt/bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoint 1 to 14 42 to 4f - read control out status endpoint status register endpoint 0 out 50 read 1 word read control in status endpoint status register endpoint 0 in 51 read 1 word read endpoint n status (n = 1 to 14) endpoint status register n endpoint 1 to 14 52 to 5f read 1 word validate control out buffer illegal: in endpoints only [2] (60) - validate control in buffer fifo endpoint 0 in [2] 61 none validate endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) [2] 62 to 6f none clear control out buffer fifo endpoint 0 out 70 none clear control in buffer illegal [3] (71) - clear endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) [3] 72 to 7f none unstall control out endpoint endpoint 0 out 80 - unstall control in endpoint endpoint 0 in 81 - unstall endpoint n (n = 1 to 14) endpoint 1 to 14 82 to 8f - check control out status [4] endpoint status image register endpoint 0 out d0 read 1 word check control in status [4] endpoint status image register endpoint 0 in d1 read 1 word check endpoint n status (n = 1 to 14) [4] endpoint status image register n endpoint 1 to 14 d2 to df read 1 word acknowledge setup endpoint 0 in and out f4 none general commands read control out error code error code register endpoint 0 out a0 read 1 word [5] read control in error code error code register endpoint 0 in a1 read 1 word [5] read endpoint n error code (n = 1 to 14) error code register endpoint 1 to 14 a2 to af read 1 word [5] unlock device all registers with write access b0 write 1 word write/read scratch register scratch register b2/b3 write/read 1 word read frame number frame number register b4 read 1 word table 74: command and register summary continued name destination code (hex) transaction [1]
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 89 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. [1] with n representing the number of bytes, the number of words for 16-bit bus width is: (n + 1) div 2. [2] validating an out endpoint buffer causes unpredictable behavior of ISP1161s dc. [3] clearing an in endpoint buffer causes unpredictable behavior of ISP1161s dc. [4] reads a copy of the status register: executing this command does not clear any status bits or interrupt bits. [5] when accessing an 8-bit register in 16-bit mode, the upper byte is invalid. [6] during isochronous transfer in 16-bit mode, because n 1023, the ?rmware must take care of the upper byte. 14.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con?gure and enable the embedded endpoints. they also serve to set the usb assigned address of ISP1161s dc and to perform a device reset. 14.1.1 write/read endpoint con?guration this command is used to access the endpoint con?guration register (ecr) of the target endpoint. it de?nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), fifo size and buffering scheme. it also enables the endpoint fifo. the register bit allocation is shown in ta b l e 7 5 . a bus reset will disable all endpoints. the allocation of fifo memory only takes place after all 16 endpoints have been con?gured in sequence (from endpoint 0 out to endpoint 14). although the control endpoints have ?xed con?gurations, they must be included in the initialization sequence and be con?gured with their default values (see ta b l e 7 ). automatic fifo allocation starts when endpoint 14 has been con?gured. remark: if any change is made to an endpoint con?guration which affects the allocated memory (size, enable/disable), the fifo memory contents of all endpoints becomes invalid. therefore, all valid data must be removed from enabled endpoints before changing the con?guration. code (hex): 20 to 2f write (control out, control in, endpoint 1 to 14) code (hex): 30 to 3f read (control out, control in, endpoint 1 to 14) transaction write/read 1 word read chip id chip id register b5 read 1 word read interrupt register interrupt register c0 read 2 words table 74: command and register summary continued name destination code (hex) transaction [1] table 75: endpoint con?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 90 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.1.2 write/read device address this command is used to set the usb assigned address in the address register and enable the usb device. the address register bit allocation is shown in ta b l e 7 7 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the address register (accessible by the microcontroller) is not altered by the bus reset. in response to the standard usb request set address the ?rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write/read address register transaction write/read 1 word 14.1.3 write/read mode register this command is used to access the ISP1161s dc mode register, which consists of 1 byte (bit allocation: see ta b l e 7 8 ). in 16-bit bus mode the upper byte is ignored. the mode register controls the dma bus width, resume and suspend modes, interrupt activity and softconnect operation. it can be used to enable debug mode, where all errors and not acknowledge (nak) conditions will generate an interrupt. code (hex): b8/b9 write/read mode register transaction write/read 1 word table 76: endpoint con?guration register: bit description bit symbol description 7 fifoen a logic 1 indicates an enabled fifo with allocated memory. a logic 0 indicates a disabled fifo (no bytes allocated). 6 epdir this bit de?nes the endpoint direction (0 = out, 1 = in); it also determines the dma transfer direction (0 = read, 1 = write) 5 dblbuf a logic 1 indicates that this endpoint has double buffering. 4 ffoiso a logic 1 indicates an isochronous endpoint. a logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] selects the fifo size according to ta b l e 8 table 77: address register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 78: address register: bit description bit symbol description 7 deven a logic 1 enables the device. 6 to 0 devadr[6:0] this ?eld speci?es the usb device address.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 91 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. [1] unchanged by a bus reset. 14.1.4 write/read hardware con?guration this command is used to access the hardware con?guration register, which consists of 2 bytes. the ?rst (lower) byte contains the device con?guration and control values, the second (upper) byte holds the clock control bits and the clock division factor. the bit allocation is given in ta b l e 8 1 . a bus reset will not change any of the programmed bit values. the hardware con?guration register controls the connection to the usb bus, clock activity and power supply during suspend state, output clock frequency, dma operating mode and pin con?gurations (polarity, signalling mode). code (hex): ba/bb write/read hardware con?guration register transaction write/read 1 word table 79: mode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol dmawd reserved gosusp reserved intena dbgmod reserved softct reset 0 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 80: mode register: bit description bit symbol description 7 dmawd a logic 1 selects 16-bit dma bus width (bus con?guration modes 0 and 2). a logic 0 selects 8-bit dma bus width. bus reset value: unchanged. 6 - reserved 5 gosusp writing a logic 1 followed by a logic 0 will activate suspend mode. 4 - reserved 3 intena a logic 1 enables all interrupts. bus reset value: unchanged. 2 dbgmod a logic 1 enables debug mode. where all naks and errors will generate an interrupt. a logic 0 selects normal operation, where interrupts are generated on every ack (bulk endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct a logic 1 enables softconnect (see section 7.5 ). this bit is ignored if extpul = 1 in the hardware con?guration register (see ta b l e 8 1 ). bus reset value: unchanged. table 81: hardware con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul nolazy clkrun ckdiv[3:0] reset 00100011 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 92 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol eotpol wkupcs pwroff intlvl intpol reset 01000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 82: hardware con?guration register: bit description bit symbol description 15 - reserved 14 extpul a logic 1 indicates that an external 1.5 k w pull-up resistor is used on pin d + and that softconnect is not used. bus reset value: unchanged. 13 nolazy a logic 1 disables output on pin clkout of the lazyclock frequency (115 khz 10 %) during suspend state. a logic 0 causes pin clkout to switch to lazyclock output after approximately 2 ms delay, following the setting of bit gosusp in the mode register. bus reset value: unchanged. 12 clkrun a logic 1 indicates that the internal clocks are always running, even during suspend state. a logic 0 switches off the internal oscillator and pll, when they are not needed. during suspend state this bit must be made logic 0 to meet the suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp in the mode register. bus reset value: unchanged. 11 to 8 ckdiv[3:0] this ?eld speci?es the clock division factor n, which controls the clock frequency on output clkout. the output frequency in mhz is given by 48 / (n + 1). the clock frequency range is 3 to 48 mhz (n = 0 to 15). with a reset value of 12 mhz (n = 3). the hardware design guarantees no glitches during frequency change. bus reset value: unchanged. 7 dakoly a logic 1 selects dack-only dma mode. a logic 0 selects 8237 compatible dma mode. bus reset value: unchanged. 6 drqpol selects dreq2 pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 5 dakpol selects dack2 pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 4 eotpol selects eot pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 3 wkupcs a logic 1 enables remote wake-up via a low level on input pin cs. bus reset value: unchanged. 2 pwroff a logic 1 enables powering-off during suspend state. output d_suspend pin is con?gured as a power switch control signal for external devices (high during suspend). this value should always be initialized to logic 1. bus reset value: unchanged. 1 intlvl selects the interrupt signalling mode on output pin int2 (0 = level, 1 = pulsed). in pulsed mode an interrupt produces an 166 ns pulse. see section 8.6.3 for details. bus reset value: unchanged. 0 intpol selects int2 pin signal polarity (0 = active low, 1 = active high). bus reset value: unchanged.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 93 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.1.5 write/read interrupt enable register this command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, sof lost, eot, suspend, resume, reset). a bus reset will not change any of the programmed bit values. the command accesses the interrupt enable register, which consists of 4 bytes. the bit allocation is given in ta b l e 8 3 . code (hex): c2/c3 write/read interrupt enable register transaction write/read 2 words table 83: interrupt enable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved reserved iepsof iesof ieeot iesusp ieresm ierst reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 84: interrupt enable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 to 10 iep14 to iep1 a logic 1 enables interrupts from the indicated endpoint. 9 iep0in a logic 1 enables interrupts from the control in endpoint. 8 iep0out a logic 1 enables interrupts from the control out endpoint. 7, 6 - reserved 5 iepsof a logic 1 enables 1 ms interrupts upon detection of pseudo sof. 4 iesof a logic 1 enables interrupt upon sof detection. 3 ieeot a logic 1 enables interrupt upon eot detection. 2 iesusp a logic 1 enables interrupt upon detection of suspend state. 1 ieresm a logic 1 enables interrupt upon detection of a resume state. 0 ierst a logic 1 enables interrupt upon detection of a bus reset.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 94 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.1.6 write/read dma con?guration this command de?nes the dma con?guration of ISP1161s dc and enables/disables dma transfers. the command accesses the dma con?guration register, which consists of 2 bytes. the bit allocation is given in ta b l e 8 5 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write/read dma con?guration transaction write/read 1 word [1] unchanged by a bus reset. for selecting an endpoint for device dma transfer, see section 11.2 . table 85: dma con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reserved reserved reserved reserved reserved reset 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dmaen reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 000 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 86: dma con?guration register: bit description bit symbol description 15 cntren a logic 1 enables the generation of an eot condition, when the dma counter register reaches zero. bus reset value: unchanged. 14 shortp a logic 1 enables short/empty packet mode. when receiving (out endpoint) a short/empty packet an eot condition is generated. when transmitting (in endpoint) this bit should be cleared. bus reset value: unchanged. 13 to 8 - reserved 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see ta b l e 1 0 . 3 dmaen writing a logic 1 enables dma transfer, a logic 0 forces the end of an ongoing dma transfer and generates an eot interrupt. reading this bit indicates whether dma is enabled (0 = dma stopped, 1 = dma enabled). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes). bus reset value: unchanged.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 95 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.1.7 write/read dma counter this command accesses the dma counter register. the bit allocation is given in ta b l e 8 7 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change the programmed bit values. the internal dma counter is automatically reloaded from the dma counter register when dma is re-enabled (dmaen = 1). see section 14.1.6 for more details. code (hex): f2/f3 write/read dma counter register transaction write/read 1 word 14.1.8 reset device this command resets the ISP1161 dc in the same way as an external hardware reset via input reset. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none 14.2 data ?ow commands data ?ow commands are used to manage the data transmission between the usb endpoints and the system microprocessor. much of the data ?ow is initiated via an interrupt to the microprocessor. the data ?ow commands are used to access the endpoints and determine whether the endpoint fifos contain valid data. remark: the in buffer of an endpoint contains input data for the host, the out buffer receives output data from the host. table 87: dma counter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacr[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 88: dma counter register: bit description bit symbol description 15 to 0 dmacr[15:0] dma counter register
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 96 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.2.1 write/read endpoint buffer this command is used to access endpoint fifo buffers for reading or writing. first, the buffer pointer is reset to the beginning of the buffer. following the command, a maximum of (m + 1) words can be written or read, with m given by (n + 1) div 2, n representing the size of the endpoint buffer. after each read/write action the buffer pointer is automatically incremented by 2. in dma access the ?rst word (the packet length) is skipped: transfers start at the second word of the endpoint buffer. when reading, the ISP1161 dc can detect the last word via the end of packet (eop) condition. when writing to a bulk/interrupt endpoint, the endpoint buffer must be completely ?lled before sending the data to the host. exception: when a dma transfer is stopped by an external eot condition, the current buffer content (full or not) is sent to the host. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command will cause unpredictable behavior of the ISP1161 dc. code (hex): 01 to 0f write (control in, endpoint 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoint 1 to 14) transaction write/read maximum (m + 1) words (isochronous endpoint: n 1023, bulk/interrupt endpoint: n 32) the data in the endpoint fifo must be organized as shown in ta b l e 8 9 . an example of endpoint fifo access is given ta b l e 9 0 . remark: there is no protection against writing or reading past a buffers boundary or against writing into an out buffer or reading from an in buffer. any of these actions could cause an incorrect operation. data residing in an out buffer are only table 89: endpoint fifo organization word # description 0 (lower byte) packet length (lower byte) 0 (upper byte) packet length (upper byte) 1 (lower byte) data byte 1 1 (upper byte) data byte 2 m = (n + 1) div 2 data byte n table 90: example of endpoint fifo access a0 phase bus lines word # description 1 command d[7:0] - command code (00h to 1fh) d[15:8] - ignored 0 data d[15:0] 0 packet length 0 data d[15:0] 1 data word 1 (data byte 2, data byte 1) 0 data d[15:0] 2 data word 2 (data byte 4, data byte 3)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 97 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. meaningful after a successful transaction. exception: during dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 14.2.2 read endpoint status this command is used to read the status of an endpoint fifo. the command accesses the endpoint status register, the bit allocation of which is shown in ta b l e 9 1 . reading the endpoint status register will clear the interrupt bit set for the corresponding endpoint in the interrupt register (see table 106 ). all bits of the endpoint status register are read-only. bit epstal is controlled by the stall/unstall commands and by the reception of a setup token (see section 14.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoint 1 to 14) transaction read 1 word table 91: endpoint status register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 92: endpoint status register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). set to logic 1 by a stall endpoint command, cleared to logic 0 by an unstall endpoint command. the endpoint is automatically unstalled upon reception of a setup token. 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the present packet (0 = data pid, 1 = data1 pid). 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1 the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 98 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.2.3 stall endpoint/unstall endpoint these commands are used to stall or unstall an endpoint. the commands modify the content of the endpoint status register (see ta b l e 9 1 ). a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the packet content. if the endpoint should stay in its stalled state, the microprocessor can re-stall it with the stall endpoint command. when a stalled endpoint is unstalled (either by the unstall endpoint command or by receiving a setup token), it is also re-initialized. this ?ushes the buffer: in and if it is an out buffer it waits for a data 0 pid, if it is an in buffer it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoint 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoint 1 to 14) transaction none 14.2.4 validate endpoint buffer this command signals the presence of valid data for transmission to the usb host, by setting the buffer full ?ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control in endpoint see section 11.3.6 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoint 1 to 14) transaction none 14.2.5 clear endpoint buffer this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ?ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control out endpoint see section 11.3.6 . code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoint 1 to 14) transaction none 14.2.6 check endpoint status this command is used to check the status of the selected endpoint fifo without clearing any status or interrupt bits. the command accesses the endpoint status image register, which contains a copy of the endpoint status register. the bit allocation of the endpoint status image register is shown in ta b l e 9 3 . code (hex): d0 to df check status (control out, control in, endpoint 1 to 14) transaction write/read 1 word
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 99 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.2.7 acknowledge setup this command acknowledges to the host that a setup packet was received. the arrival of a setup packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor needs to re-enable these commands by sending an acknowledge setup command, see section 11.3.6 . remark: the acknowledge setup command must be sent to both control endpoints (in and out). code (hex): f4 acknowledge setup transaction none 14.3 general commands 14.3.1 read endpoint error code this command returns the status of the last transaction of the selected endpoint, as stored in the error code register. each new transaction overwrites the previous status information. the bit allocation of the error code register is shown in ta b l e 9 5 . code (hex): a0 to af read error code (control out, control in, endpoint 1 to 14) table 93: endpoint status image register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 94: endpoint status image register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the present packet (0 = data pid, 1 = data1 pid). 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1 the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 100 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. transaction read 1 word 14.3.2 unlock device this command unlocks ISP1161s dc from write-protection mode after a resume. in suspend state all registers and fifos are write-protected to prevent data corruption by external devices during a resume. register access for reading is not blocked. table 95: error code register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00000000 access rrrrrrrr table 96: error code register: bit description bit symbol description 7 unread a logic 1 indicates that a new event occurred before the previous status was read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid, 1 = data1 pid). 5 - reserved 4 to 1 error[3:0] error code. for error description, see ta b l e 9 7 . 0 rtok a logic 1 indicates that data was received or transmitted successfully. table 97: transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a setup token to a non-control endpoint 0100 token crc error 0101 data crc error 0110 time-out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over?ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf?ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 101 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. after waking up from suspend state, the ?rmware must unlock the registers and fifos via this command, by writing the unlock code (aa37h) into the lock register. the bit allocation of the lock register is given in ta b l e 9 8 . code (hex): b0 unlock the device transaction write 1 word (unlock code) 14.3.3 write/read scratch register this command accesses the 16-bit scratch register, which can be used by the ?rmware to save and restore information, e.g., the device status before powering down in suspend state. the register bit allocation is given in table 100 . code (hex): b2/b3 write/read scratch register transaction write/read 1 word table 98: lock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlockh[7:0] = aah reset 10101010 access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol unlockl[7:0] = 37h reset 00110111 access wwwwwwww table 99: lock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks the internal registers and fifos for writing, following a resume. table 100:scratch information register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sfirh[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 101:scratch information register: bit description bit symbol description 15 - reserved; must be logic 0 14 to 0 sfir[14:0] scratch information register
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 102 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.3.4 read frame number this command returns the frame number of the last successfully received sof. it is followed by reading one word from the frame number register, containing the frame number. the frame number register is shown in table 102 . remark: after a bus reset, the value of the frame number register is unde?ned. code (hex): b4 read frame number transaction read 1 word [1] reset value unde?ned after a bus reset. 14.3.5 read chip id this command reads the chip identi?cation code and hardware version number. the ?rmware must check this information to determine the supported functions and features. this command accesses the chip id register, which is shown in table 104 . code (hex): b5 read chip id transaction read 1 word table 102:frame number register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reserved reserved reserved reserved sofrh[2:0] reset [1] 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofrl[7:0] reset [1] 00000000 access rrrrrrrr table 103:example of frame number register access a0 phase bus lines word # description 1 command d[7:0] - command code (b4h) d[15:8] - ignored 0 data d[15:0] 0 frame number table 104:chip id register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 01100001 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset x0h access rrrrrrrr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 103 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 14.3.6 read interrupt register this command indicates the sources of interrupts as stored in the 4-byte interrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the interrupt register is shown in table 106 . bit bustatus is used to verify the current bus status in the interrupt service routine. interrupts are enabled via the interrupt enable register, see section 14.1.5 . while reading the interrupt register, please read both 2 bytes completely. code (hex): c0 read interrupt register transaction read 2 words table 105:chip id register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (61h) 7 to 0 chipidl[7:0] silicon version (xxh, with xx representing the bcd encoded version number) table 106:interrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reserved reserved reserved reserved reserved reserved reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus reserved psof sof eot suspnd resume reset reset 00000000 access rrrrrrrr table 107: interrupt register: bit description bit symbol description 31 to 24 - reserved 23 to 10 ep14 to ep1 a logic 1 indicates the interrupt source(s): endpoint 14 to 1 9 ep0in a logic 1 indicates the interrupt source: control in endpoint 8 ep0out a logic 1 indicates the interrupt source: control out endpoint 7 bustatus monitors the current usb bus status (0 = awake, 1 = suspend). 6 - reserved
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 104 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 15. reset pin reset is the hardware reset input of ISP1161. it is active low. to reset all internal logic, the minimum timing requirement is 200 ns. 16. power supply ISP1161 can operate at either +5 v or +3.3 v. when using +5 v as ISP1161s power supply input: only v cc (pin 56) can be connected to the +5 v power supply. an application with a +5 v power supply input is shown in figure 41 . ISP1161 has an internal dc/dc regulator to provide +3.3 v for its internal core. this internal +3.3 v can also be obtained from v reg(3.3) (pin 58) to supply the 1.5 k w pull-up resistor of the dc side upstream port signal d_dp. the signal d_dp is connected to the standard usb upstream port connectors pin d+. when using +3.3 v as the power supply input, the internal dc/dc regulator will be bypassed. all four power supply pins (v cc ,v reg(3.3) ,v hold1 and v hold2 ) can be used as power supply input. the best case is to connect all four power supply pins to the +3.3 v power supply, as shown in figure 42 . if, however you do not want to connect all four, you must at least, connect the v cc and the v reg(3.3) to the 3.3 v power supply. for both +3.3 v and 5 v operation, all four power supply pins should be connected to a decoupling capacitor. 5 psof a logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after 3 missed sofs suspend state is entered. 4 sof a logic 1 indicates that a sof condition was detected. 3 eot a logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd a logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume a logic 1 indicates that a resume state was detected. 0 reset a logic 1 indicates that a bus reset condition was detected. table 107: interrupt register: bit description continued bit symbol description fig 40. reset pin usage. mgt962 reset reset from m p or not connected v cc ISP1161
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 105 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 17. external clock input the ISP1161 has a crystal oscillator designed for a 6 mhz parallel-resonant crystal (fundamental). a typical circuit is shown in figure 43 . alternatively, an external clock signal of 6 mhz can be applied to in put xtal1, while leaving output xtal2 open. see figure 44 . the 6 mhz oscillator frequency is multiplied to 48 mhz by an internal pll. this frequency is used to generate a programmable clock output signal at pin clkout, ranging from 3 to 48 mhz. fig 41. using a +5 v supply. fig 42. using a +3.3 v supply. mgt963 1.5 k w d_dp gnd v cc v reg(3.3) v hold1 v hold2 to usb upstream port connector + 5 v ISP1161 mgt964 1.5 k w d_dp gnd v cc v reg(3.3) v hold1 v hold2 to usb upstream port connector + 3.3 v ISP1161 fig 43. oscillator circuit with external crystal. fig 44. oscillator circuit using external oscillator. 18 pf 6 mhz 18 pf mgt965 clkout xtal2 xtal1 ISP1161 osc out n.c. 6 mhz mgt966 clkout xtal2 xtal1 ISP1161 v cc
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 106 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 18. limiting values [1] equivalent to discharging a 100 pf capacitor via a 1.5 k w resistor (human body model). [2] values are given for device only; in-circuit v esd(max) = 8000 v. [1] 5 v tolerant. table 108:absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(5v) supply voltage to v cc pin - 0.5 + 6.0 v v cc(3.3v) supply voltage to v reg(3.3) pin - 0.5 +4.6 v v i input voltage - 0.5 +6.0 v i latchup latchup current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <10 m a [1] [2] - 2000 v t stg storage temperature - 60 + 150 c table 109:recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage with internal regulator 4.0 5.0 5.5 v internal regulator bypass 3.0 3.3 3.6 v v i input voltage 0 v cc 5.5 [1] v v i(a i/o) input voltage on analog i/o pins (d + / d - ) 0 - 3.6 v v o(od) open-drain output pull-up voltage 0 - v cc v t amb operating ambient temperature - 40 - + 85 c
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 107 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 19. static characteristics [1] in suspend mode, the minimum voltage is 2.7 v. [1] not applicable for open-drain outputs. table 110:static characteristics; supply pins v cc = 3.0 to 3.6 v or 4.0 to 5.5 v; v gnd =0v; t amb = - 40 to + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v cc =+5v v reg(3.3) internal regulator output 3.0 [1] 3.3 3.6 v i cc operating supply current - 47 - ma i cc(susp ) suspend supply current - 40 500 m a i cc(hc ) operating supply current for hc dc is suspended - 22 - ma i cc(dc ) operating supply current for dc hc is suspended - 18 - ma v cc = +3.3 v i cc operating supply current - 50 - ma i cc(susp ) suspend supply current - 150 - m a i cc(hc ) operating supply current for hc dc is suspended - 22 - ma i cc(dc ) operating supply current for dc hc is suspended - 18 - ma table 111:static characteristics: digital pins v cc = 3.0 to 3.6 v or 4.0 to 5.5 v; v gnd =0v; t amb = - 40 to + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = rated drive - - 0.4 v i ol =20 m a - - 0.1 v v oh high-level output voltage i oh = rated drive [1] 2.4 - - v i oh =20 m av reg(3.3) - 0.1 - - v leakage current i li input leakage current - - 5 m a c in pin capacitance pin to gnd - - 5 pf open-drain outputs i oz off-state output current - - 5 m a
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 108 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. [1] d + is the usb positive data pin; d - is the usb negative data pin. [2] includes external resistors of 18 w 1% on both h_d + and h_d - . [3] in suspend mode, the minimum voltage is 2.7 v. table 112:static characteristics: analog i/o pins (d + , d - ) v cc = 3.0 to 3.6 v or 4.0 to 5.5 v; v gnd =0v; t amb = - 40 to + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d + ) - v i(d - ) | [1] 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to + 3.6 v - - 0.3 v v oh high-level output voltage r l =15k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current - - 10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance r pd pull-down resistance on hcs dp/dm enable internal resistors 11 - 19 k w r pu pull-up resistance on d_dp softconnect = on 1.1 - 1.9 k w z drv driver output impedance steady-state drive [2] 29 - 44 w z inp input impedance 10 - - m w termination v term termination voltage for upstream port pull-up (r pu ) 3.0 [3] - 3.6 v
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 109 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [1] test circuit; see figure 57 . [2] excluding the ?rst transition from idle state. [3] characterized only, not tested. limits guaranteed by design. table 113:dynamic characteristics v cc = 3.0 to 3.6 v or 4.0 to 5.5 v; v gnd =0v; t amb = - 40 to + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w( reset) pulse width on input reset crystal oscillator running 50 - - m s crystal oscillator stopped - [1] -ms crystal oscillator f xtal crystal frequency - 6 - mhz table 114:dynamic characteristics: analog i/o pins (d + , d - ) [1] v cc = 3.0 to 3.6 v or 4.0 to 5.5 v; v gnd =0v; t amb = - 40 to + 85 c; c l = 50 pf; r pu = 1.5 k w 5% on d + to v term ; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l =50pf; 10 to 90% of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90 to 10% of | v oh - v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2] [3] 1.3 - 2.0 v
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 110 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.1 timing symbols table 115:legend for timing characteristics symbol description time symbols t time t cycle time (periodic signal) signal names a address; dma acknowledge (dack) c clock; command d data input; data e chip enable g output enable i instruction (program memory content); input (general) l address latch enable (ale) p program store enable ( psen, active low); propagation delay q data output r read signal ( rd, active low); read (action); dma request (dreq) s chip select w write signal ( wr, active low); write (action); pulse width u unde?ned y output (general) logic levels h logic high l logic low p stop, not active (off) s start, active (on) v valid logic level x invalid logic level z high-impedance (?oating, three-state)
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 111 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.2 parallel i/o timing table 116:dynamic characteristics: parallel interface timing symbol parameter conditions 16-bit bus unit min max read timing t shsl ?rst rd/wr after cmd 300 - ns t slrl cs low to rd low 0 - ns t rhsh rd high to cs high 0 - ns t rl rd low pulse width 33 - ns t rhrl rd high to next rd low 110 - ns t rc rd cycle 143 - ns t rhdz rd data hold time 3 - ns t rldv rd low to data valid 32 - ns write timing t wl wr low pulse width 26 - ns t whwl wr high to next wr low 110 - ns t wc wr cycle 136 - ns t slwl cs low to wr low 0 - ns t whsh wr high to cs high 0 - ns t wdsu wr data setup time 5 - ns t wdh wr data hold time 8 - fig 45. 16-bit microprocessor parallel i/o interface timing. mgt969 a0 d [ 15:0 ] d[15:0] wr rd cs data valid data valid data valid data valid data valid data valid data valid data valid data valid t shsl t rl t rhrl t rldv t wl t whwl t wdh t wdsu t rc t wc t rhdz t slrl t rhsh t slwl t whsh
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 112 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.3 dma interface timing 20.3.1 hc single-cycle burst mode dma timing [1] t rhal +t ds +t alrl . table 117:dynamic characteristics: hc single-cycle burst mode dma timing symbol parameter conditions 16-bit bus unit min max read/write timing t rl rd pulse width 33 - ns t rldv read process data setup time 26 - ns t rhdz read process data hold time 0 - ns t wsu write process data setup time 5 - ns t whd write process data hold time 0 - ns t ahrh dack1 high to dreq1 high 62 to 81 - ns t alrl dack1 low to dreq1 low - 21 ns t dc dreq1 cycle [1] -ns t shah rd/wr high to dack1 high > 0 - ns t rhal dreq1 high to dack1 low > 0 - ns t ds dreq1 pulse spacing 125 to 146 - ns fig 46. hc single-cycle burst mode dma timing. mgt970 dreq1 dack1 d [ 15:0 ] (read) d [ 15:0 ] (write) rd or wr t ds t ahrh t dc data valid data valid t alrl t rhal t whd t wsu t rldv t rhdz t shah
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 113 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.3.2 hc multi-cycle burst mode dma timing [1] t slal + (4 or 8)t rc + t ds . table 118:dynamic characteristics: hc multi-cycle burst mode dma timing symbol parameter conditions 16-bit bus unit min max read/write timing (for 4-cycle and 8-cycle burst mode) t rl wr/rd low pulse width 42 - ns t rhrl wr/rd high to next wr/rd low 60 - ns t rc wr/rd cycle 102 - ns t slrl rd/wr low to dreq1 low 22 64 ns t shah rd/wr high to dack1 high > 0 - ns t rhal dreq1 high to dack1 low > 0 t dc dreq1 cycle [1] -ns t ds(read) dreq1 pulse spacing (read) 4-cycle burst mode 105 - t ds(read) dreq1 pulse spacing (read) 8-cycle burst mode 150 - t ds(write) dreq1 pulse spacing (write) 4-cycle burst mode 62 to 84 - ns t ds(write) dreq1 pulse spacing (write) 8-cycle burst mode 150 to 167 - ns fig 47. hc multi-cycle burst mode dma timing. mgt971 t rhrl t ds t rhsh dreq1 dack1 rd or wr t slrl t shah t rl t rc t slal
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 114 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.3.3 external eot timing for hc single-cycle burst mode dma 20.3.4 external eot timing for hc multi-cycle burst mode dma 20.3.5 dc single-cycle dma timing (8237 mode) fig 48. external eot timing for hc single-cycle burst mode dma. mgt972 dreq1 dack1 eot t el > 0 ns rd or wr fig 49. external eot timing for hc multi-cycle burst mode dma. mgt973 dreq1 dack1 eot t el > 0 ns rd or wr table 119:dynamic characteristics: dc single-cycle dma timing (8237 mode) symbol parameter conditions min typ max unit t alrl dack2 on to dreq2 off - - 40 ns t ahrh dack2 off to dreq2 on - - 22 ns fig 50. dc single-cycle dma timing (8237 mode). mgt974 dreq2 dack2 t ahrh t alrl
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 115 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.3.6 dc single-cycle dma timing (dack-only mode) 20.3.7 eot timing for dc single-cycle dma timing table 120:dynamic characteristics: dc single-cycle dma timing (dack-only mode) symbol parameter conditions min typ max unit t alrl dack2 on to dreq2 off - - 40 ns t ahrh dack2 off to dreq2 on - - 22 ns t aldv dack2 on to data valid - - 22 ns t ahdz dack2 off to data invalid - - 3 ns fig 51. dc single-cycle dma timing (dack-only mode). mgt975 dreq2 dack2 d [ 15:0 ] t ahrh t alrl t aldv t ahdz table 121:dynamic characteristics: eot timing for dc single-cycle dma timing symbol parameter conditions min typ max unit t rhsh dreq2 on to rd/wr off 22 - - ns t ahrh dack2 off to dreq2 on - - 22 ns t shah rd/wr off to dack2 off 0 - - ns t el eot pulse width 22 - - ns fig 52. eot timing for dc single-cycle dma timing. mgt976 t ahrh t rhsh t shah t el dreq2 dack2 eot rd or wr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 116 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 20.3.8 dc multi-cycle burst mode dma timing 20.3.9 dma terminated by eot table 122:dynamic characteristics: dc multi-cycle burst mode dma timing symbol parameter conditions min typ max unit t rhsh dreq2 on to ?rst rd/wr off 22 - - ns t slrl last rd/wr on to dreq2 off - - 60 ns t shah last rd/wr off to dack2 off 0 - - ns t rhrl dma burst repeat interval 180 - - ns fig 53. dc multi-cycle burst mode dma timing. mgt977 t rhsh t slrl t rhrl t shah dreq2 dack2 rd or wr table 123:dynamic characteristics: dma terminated by eot symbol parameter conditions min typ max unit t elrl eot on to dreq2 off - - 40 ns fig 54. dma terminated by eot. mgt978 t elrl dreq2 dack2 eot rd or wr
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 117 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 21. application information 21.1 typical interface circuit for mosfet, r dson = 150 m w . fig 55. typical interface circuit to hitachi sh-3 (sh7709) risc processor. mgt979 1 k w 1.5 k w led fb4 fb6 fb3 fb2 fb1 22 w (2 ) 22 pf 22 pf 47 pf (2 ) + 5 v + 3.3 v + 3.3 v + 5 v v dd + 5 v + 5 v vbus_dn2 vbus_dn1 + 3.3 v + 5 v sh7709 a1 a0 mosfet (2 ) usb downstrea m port #1 usb downstrea m port #2 d [ 15:0 ] d [ 15:0 ] a2 a1 dreq0 dreq1 dack0 dack1 dreq1 dreq2 cs5 cs rd rd rd/wr wr dack1 dack2 eot ptc0 h_wakeup ptc1 h_suspend ptc2 d_wakeup ptc3 d_suspend gnd xtal2 extal2 32 khz 6 mhz xtal extal dgnd agnd irq2 int1 irq3 int2 rstout reset ISP1161 clkout clkout h_oc1 h_oc2 h_psw2 h_psw1 v cc v reg(3.3) v hold1 v hold2 h_dm1 h_dp1 h_dm2 h_dp2 d_dm d_dp ndp_sel gl d_vbus clkout xtal2 xtal1 v reg v dd v dd + 3.3 v v reg usb upstream port 22 w (2 ) 47 pf (2 ) vbus_up fb5 22 w (2 ) 47 pf (2 ) 7
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 118 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 21.2 interfacing a ISP1161 with a sh7709 risc processor this section shows a typical interface circuit between ISP1161 and a risc processor. the hitachi sh-3 series risc processor sh7709 is used as the example. the main ISP1161 signals to be taken into consideration for connecting to a sh7709 risc processor are: ? a 16-bit data bus: d15-d0 for ISP1161. ISP1161 is little endian compatible. ? two address lines a1 and a0 are needed for a complete addressing of the ISP1161 internal registers: C a1 = 0 and a0 = 0 will select the data port of the host controller C a1 = 0 and a0 = 1 will select the command port of the host controller C a1 = 1 and a0 = 0 will select the data port of the device controller C a1 = 1 and a0 = 1 will select the command port of the device controller ? the cs line is used for chip selection of ISP1161 in a certain address range of the risc system. this signal is active low. ? rd and wr are common read and write signals. these signals are active low. ? there are two dma channel standard control lines: C dreq1 and dack1 C dreq2 and dack2 (in each case one channel is used by the host controller and the other channel is used by the device controller). these signals have programmable active levels. ? two interrupt lines: int1 (used by the host controller) and int2 (used by the device controller). both have programmable level/edge and polarity (active high or low). ? the internal 15k w pull-down resistors are used for the hcs two usb downstream ports. ? the reset signal is active low. remark: sh7709s system clock input is for reference only. please refer to sh7709s speci?cation for its actual use. ISP1161 can work under either +3.3 v or +5.0 v power supply; however, its internal core actually works at +3.3 v. when using +5 v as the power supply input, the internal dc/dc regulator will be bypassed. it is best to connect all four power supply pins (v cc , v reg(3.3) , v hold1 and v hold2 ) to the 3.3 v power supply (for more information see section 16 ). all of the ISP1161s i/o pins are +5 v-tolerant. this feature allows the ISP1161 the ?exibility to be used in an embedded system under either a +3.3 v or a +5 v power supply. a typical sh7709 interface circuit is shown in figure 55 . 21.3 typical software model this section shows a typical software requirement for an embedded system that incorporates ISP1161. the software model for a digital still camera (dsc) is used as the example for illustration (as shown in figure 56 ). two components of system software are required to make full use of the features in ISP1161: the host stack and
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 119 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. the device stack. the device stack provides api directly to the application task for device function; the host stack provides api for class driver and device driver, both of which provide api for application tasks for host function. 22. test information the dynamic characteristics of the analog i/o ports (d + and d -) as listed in table 114 were determined using the circuit shown in figure 57 . fig 56. ISP1161 software model for dsc application. printer pc flash card reader/ writer usb upstream usb downstream digital still camera risc rom ram ISP1161 len control mgt980 mechanism control task image processing tasks file management os printer ui/control printing class driver host stack device stack usb host/device stack class driver application layer file transfer device drivers mass storage class driver ISP1161 hal
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 120 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. load capacitance: c l = 50 pf (full-speed mode). speed: full-speed mode only: internal 1.5 k w pull-up resistor on d_dp. fig 57. load impedance for d_dp and d_dm pins. mgt967 15 k w 22 w test point c l 50 pf d.u.t.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 121 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 23. package outline fig 58. lqfp64 (sot314-2) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 99-12-27 00-01-19 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 122 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. fig 59. lqfp64 (sot414-1) package outline. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 0.4 9.15 8.85 0.64 0.36 7 0 o o 0.08 0.08 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot414-1 136e06 ms-026 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.64 0.36 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm sot414-1
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 123 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. 24. soldering 24.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 24.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c small/thin packages. 24.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 124 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 24.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 24.5 package related soldering information [1] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [2] these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). [3] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [4] wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [5] wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 25. revision history table 124:suitability of surface mount ic packages for wave and re?ow soldering methods package soldering method wave re?ow [1] bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable [2] suitable plcc [3] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [3] [4] suitable ssop, tssop, vso not recommended [5] suitable table 125:revision history rev date cpcn description 01 20010703 - product data; initial version.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 125 of 130 9397 750 08313 ? philips electronics n.v. 2001 all rights reserved. 26. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is ava ilable on the internet at url http://www.semiconductors.philips.com. 27. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 28. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 29. trademarks goodlink is a trademark of koninklijke philips electronics n.v. hitachi is a registered trademark of hitachi ltd. softconnect is a trademark of koninklijke philips electronics n.v. arm is a trademark of arm holdings plc. strongarm is a trademark of arm holdings plc. data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
philips semiconductors ISP1161 full-speed usb single-chip host and device controller product data rev. 01 3 july 2001 126 of 130 9397 750 08313 ? philips electronics n.v. 2001. all rights reserved. philips semiconductors - a worldwide company argentina: see south america australia: tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: tel. +43 160 101, fax. +43 160 101 1210 belarus: tel. +375 17 220 0733, fax. +375 17 220 0773 belgium: see the netherlands brazil: see south america bulgaria: tel. +359 268 9211, fax. +359 268 9102 canada: tel. +1 800 234 7381 china/hong kong: tel. +852 2 319 7888, fax. +852 2 319 7700 colombia: see south america czech republic: see austria denmark: tel. +45 3 288 2636, fax. +45 3 157 0044 finland: tel. +358 961 5800, fax. +358 96 158 0920 france: tel. +33 1 4728 6600, fax. +33 1 4728 6638 germany: tel. +49 40 23 5360, fax. +49 402 353 6300 hungary: tel. +36 1 382 1700, fax. +36 1 382 1800 india: tel. +91 22 493 8541, fax. +91 22 493 8722 indonesia: see singapore ireland: tel. +353 17 64 0000, fax. +353 17 64 0200 israel: tel. +972 36 45 0444, fax. +972 36 49 1007 italy: tel. +39 039 203 6838, fax +39 039 203 6800 japan: tel. +81 33 740 5130, fax. +81 3 3740 5057 korea: tel. +82 27 09 1412, fax. +82 27 09 1415 malaysia: tel. +60 37 50 5214, fax. +60 37 57 4880 mexico: tel. +9-5 800 234 7381 middle east: see italy netherlands: tel. +31 40 278 2785, fax. +31 40 278 8399 new zealand: tel. +64 98 49 4160, fax. +64 98 49 7811 norway: tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: tel. +63 28 16 6380, fax. +63 28 17 3474 poland: tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: tel. +27 11 471 5401, fax. +27 11 471 5398 south america: tel. +55 11 821 2333, fax. +55 11 829 1849 spain: tel. +34 33 01 6312, fax. +34 33 01 4107 sweden: tel. +46 86 32 2000, fax. +46 86 32 2745 switzerland: tel. +41 14 88 2686, fax. +41 14 81 7730 taiwan: tel. +886 22 134 2451, fax. +886 22 134 2874 thailand: tel. +66 23 61 7910, fax. +66 23 98 3447 turkey: tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine: tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: tel. +44 208 730 5000, fax. +44 208 754 8421 united states: tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: tel. +381 11 3341 299, fax. +381 11 3342 553 for all other countries apply to: philips semiconductors, marketing communications, building be, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 272 4825 internet: http://www.semiconductors.philips.com (sca72)
? philips electronics n.v. 2001. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 3 july 2001 document order number: 9397 750 08313 contents philips semiconductors ISP1161 full-speed usb single-chip host and device controller 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 11 7.1 pll clock multiplier. . . . . . . . . . . . . . . . . . . . . 11 7.2 bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11 7.3 analog transceivers . . . . . . . . . . . . . . . . . . . . 11 7.4 philips serial interface engine (sie). . . . . . . . 11 7.5 softconnect (in dc) . . . . . . . . . . . . . . . . . . . . 11 7.6 goodlink (in dc) . . . . . . . . . . . . . . . . . . . . . . 12 7.7 suspend and wakeup (in dc). . . . . . . . . . . . . 12 8 microprocessor bus interface . . . . . . . . . . . . . 12 8.1 i/o addressing mode . . . . . . . . . . . . . . . . . . . 12 8.2 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3 microprocessor read/write ISP1161s internal control registers by pio mode . . . . . 14 8.4 microprocessor read/write ISP1161s internal fifo buffer ram by pio mode. . . . . 17 8.5 microprocessor read/write ISP1161s internal fifo buffer ram by dma mode. . . . 17 8.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 the usb host controller (hc) . . . . . . . . . . . . . 22 9.1 the hcs four usb states. . . . . . . . . . . . . . . . 22 9.2 generating usb traffic . . . . . . . . . . . . . . . . . . 22 9.3 ptd data structure . . . . . . . . . . . . . . . . . . . . . 24 9.4 hcs internal fifo buffer ram structure . . . . 27 9.5 hcs operational model . . . . . . . . . . . . . . . . . 33 9.6 microprocessor loading. . . . . . . . . . . . . . . . . . 36 9.7 internal 15 kw pull-down resistors for downstream ports . . . . . . . . . . . . . . . . . . . . . 36 9.8 overcurrent detection and power switching control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 suspend and wakeup (in hc) . . . . . . . . . . . . . 40 10.1 hc suspended state . . . . . . . . . . . . . . . . . . . . 40 10.2 hc wakeup from suspended state . . . . . . . . . 41 11 the usb device controller (dc) . . . . . . . . . . . 42 11.1 dc data transfer operation . . . . . . . . . . . . . . . 42 11.2 device dma transfer. . . . . . . . . . . . . . . . . . . . 43 11.3 endpoint descriptions . . . . . . . . . . . . . . . . . . . 44 12 dma transfer for the device controller . . . . . 48 12.1 selecting an endpoint for dma transfer . . . . . 48 12.2 8237 compatible mode . . . . . . . . . . . . . . . . . . 49 12.3 dack-only mode . . . . . . . . . . . . . . . . . . . . . . 50 12.4 end-of-transfer conditions. . . . . . . . . . . . . . . 51 13 hc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.1 hc control and status registers. . . . . . . . . . . . 54 13.2 hc frame counter registers. . . . . . . . . . . . . . . 62 13.3 hc root hub registers . . . . . . . . . . . . . . . . . . 66 13.4 hc dma and interrupt control registers . . . . . 76 13.5 hc miscellaneous registers . . . . . . . . . . . . . . 81 13.6 hc buffer ram control registers . . . . . . . . . . . 82 14 dc commands and registers . . . . . . . . . . . . . 86 14.1 initialization commands. . . . . . . . . . . . . . . . . . 89 14.2 data flow commands . . . . . . . . . . . . . . . . . . . 96 14.3 general commands. . . . . . . . . . . . . . . . . . . . 100 15 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 105 17 external clock input . . . . . . . . . . . . . . . . . . . . 106 18 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 107 19 static characteristics . . . . . . . . . . . . . . . . . . . 108 20 dynamic characteristics . . . . . . . . . . . . . . . . 111 20.1 timing symbols . . . . . . . . . . . . . . . . . . . . . . . 112 20.2 parallel i/o timing . . . . . . . . . . . . . . . . . . . . . 113 20.3 dma interface timing. . . . . . . . . . . . . . . . . . . 114 21 application information . . . . . . . . . . . . . . . . . 119 21.1 typical interface circuit . . . . . . . . . . . . . . . . . 119 21.2 interfacing a ISP1161 with a sh7709 risc processor . . . . . . . . . . . . . . . . . . . . . . 120 21.3 typical software model . . . . . . . . . . . . . . . . . 120 22 test information . . . . . . . . . . . . . . . . . . . . . . . 121 23 package outline . . . . . . . . . . . . . . . . . . . . . . . 123 24 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 24.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 24.2 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 125 24.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 125 24.4 manual soldering. . . . . . . . . . . . . . . . . . . . . . 126 24.5 package related soldering information . . . . . 126 25 revision history . . . . . . . . . . . . . . . . . . . . . . . 126 26 data sheet status . . . . . . . . . . . . . . . . . . . . . . 127 27 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 28 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 29 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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